Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQXTN (H)

Test 1: uops

Code:

  uqxtn b0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254725100010001000398160301830373037241432895100010001000303730371110011000073216222629100030383038303830383038
1004303722661254725100010001000398160301830373037241432895100010001000303730371110011000073216222629100030383038303830383038
1004303722061254725100010001000398160301830373037241432895100010001000303730371110011000073216222629100030383038303830383038
1004303723061254725100010001000398160301830373037241432895100010001000303730371110011000073216222629100030383038303830383038
1004303723061254725100010001000398160301830373037241432895100010001000303730371110011000073216222629100030383038303830383038
1004303723061254725100010001000398160301830373037241432895100010001000303730371110011000073216222629100030383038303830383038
1004303723061254725100010001000398160301830373037241432895100010001000303730371110011000073216222629100030383038303830383038
1004303722061254725100010001000398160301830373037241432895100010001000303730371110011000073216222629100030383038303830383038
1004303723061254725100010001000398160301830373037241432895100010001000303730371110011000073216222629100030383038303830383038
1004303722061254725100010001000398160301830373037241432895100010001000303730371110011000073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  uqxtn b0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
1020430037225000005692954725101001001000010010000500427716013001830037300372826432876710100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
102043003722400060612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300372110201100991001001000010000000071011611296330100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
102043003722500000822954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
102043003722500000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722400000000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
1002430037224000000000168295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003722500000000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629210000103003830038300383003830038
100243003722500000060082295472510010101000010100005542771600300183003730037282863287671001020100002010329300373003711100211091010100001000000007252162229629010000103003830038300383003830038
100243003722500000000145922948415310069131006412110508242825680300183003730037282863287671001020100002010000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
1002430037224000052801528039852946615210077161007212111597742879760302703041030463283173628933113462211308261130530413303699110021109101010000102000022190081051064429960310000103055730560305103052130550
10024305112290111101013325280779295202510092221008014116236642906800300223003730037282863287671001020100002010000300373003711100211091010100001000000006403402229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  uqxtn b0, h8
  uqxtn b1, h8
  uqxtn b2, h8
  uqxtn b3, h8
  uqxtn b4, h8
  uqxtn b5, h8
  uqxtn b6, h8
  uqxtn b7, h8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059152110267258010810080212101801305006409961200682003920039998612999080232200800322008003220039200391180201100991001008000010030231115118160020036800001002004020040200402004020040
802042003915000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000661115118160020036800001002004020040200402004020040
80204200391500003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118160020036800001002004020040200402004020040
80204200391500003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000331115118160020036800001002004020040200402004020040
802042003915000022025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000091115118160020036800001002004020040200402004020040
80204200391500003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000031115118160020036800001002004020040200402004020040
80204200391500005325801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000031115118160020036800001002004020040200402004020040
80204200391500003025801081008000810280020500640132020020200392009999776999080120200800322008003220039200911180201100991001008000010002061115136411020036800001002015320142200402004020040
80204200391500003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000061115118160020036800001002004020040200402004020040
80204200391500003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010001061115118160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200501500402580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010005020121612122003680000102004020040200402004020040
80024200391500402580010108000010800005064000002002032003920039999631001980010208000020800002003920039118002110910108000010005020121612122003680000102004020040200402004020040
80024200391500402580010108000010800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010035020131612122003680000102004020040200402004020040
80024200391500402580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010005020121611122003680000102004020040200402004020040
80024200391500402580010108000010800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010005020121611132003680000102004020040200402004020040
80024200391500402580010108000010800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010105020111611112003680000102004020090200402004020040
80024200391500402580010108000010800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010195020111612132003680000102004020040200402004020040
80024200391500402580010108000010800005064000002002002003920039999631001980010208000020800002003920039118002110910108000010005020111611112003680000102004020040200402004020040
800242003915002302580010108029310800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010365020121613122003680000102004020040200402004020040
80024200391500402580010108000010800005064000012002002003920039999631001980010208000020800002003920039118002110910108000010005020121611112003680000102004020040200402004020040