Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
uqxtn h0, s0
movi v0.16b, 1 movi v1.16b, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule simd uop (54) | dispatch simd uop (57) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map simd uop (7e) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd alu (9a) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
1004 | 3037 | 22 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2415 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 3 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 22 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 23 | 0 | 82 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 23 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 23 | 0 | 312 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 23 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 23 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 22 | 0 | 390 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 23 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 6 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
1004 | 3037 | 23 | 0 | 61 | 2547 | 25 | 1000 | 1000 | 1000 | 398160 | 0 | 3018 | 3037 | 3037 | 2414 | 3 | 2895 | 1000 | 1000 | 1000 | 3037 | 3037 | 1 | 1 | 1001 | 1000 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 2629 | 1000 | 3038 | 3038 | 3038 | 3038 | 3038 |
Code:
uqxtn h0, s0
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0037
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 189 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 0 | 30018 | 30181 | 30037 | 28264 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30084 | 226 | 0 | 0 | 0 | 0 | 0 | 69 | 0 | 1455 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 0 | 30018 | 30037 | 30037 | 28264 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 5 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29547 | 86 | 10100 | 110 | 10000 | 103 | 10000 | 500 | 4277160 | 0 | 30018 | 30037 | 30037 | 28264 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 1 | 2 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29547 | 80 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 0 | 30018 | 30037 | 30037 | 28264 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 5 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 0 | 30018 | 30037 | 30037 | 28264 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 4 | 2 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 103 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 0 | 30018 | 30037 | 30037 | 28264 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 1 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 1 | 30018 | 30037 | 30037 | 28264 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 103 | 29547 | 100 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 0 | 30018 | 30037 | 30037 | 28264 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 3 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 0 | 30018 | 30037 | 30037 | 28264 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 1 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
10204 | 30037 | 224 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29547 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 4277160 | 0 | 30018 | 30037 | 30131 | 28264 | 3 | 28745 | 10100 | 200 | 10000 | 200 | 10000 | 30037 | 30037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 29633 | 0 | 10000 | 100 | 30038 | 30038 | 30038 | 30038 | 30038 |
Result (median cycles for code): 3.0037
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb miss (a1) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | c2 | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277160 | 30018 | 30037 | 30037 | 28286 | 0 | 26 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 3 | 0 | 9 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277160 | 30018 | 30037 | 30037 | 28286 | 0 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277160 | 30018 | 30037 | 30037 | 28286 | 0 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4277160 | 30018 | 30037 | 30037 | 28286 | 0 | 3 | 28767 | 10010 | 20 | 10000 | 20 | 10000 | 30037 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | 640 | 2 | 16 | 4 | 3 | 29901 | 1 | 10000 | 10 | 30413 | 30416 | 30170 | 30417 | 30416 |
10024 | 30418 | 228 | 1 | 1 | 9 | 8 | 399 | 792 | 5180 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4278512 | 30018 | 30037 | 30037 | 28312 | 0 | 42 | 28915 | 11364 | 24 | 11141 | 20 | 11306 | 30177 | 30037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 45 | 2 | 24813 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 3905 | 29484 | 177 | 10079 | 16 | 10056 | 14 | 11050 | 67 | 4285272 | 30306 | 30464 | 30179 | 28317 | 0 | 34 | 28917 | 11063 | 22 | 11303 | 24 | 10652 | 30413 | 30418 | 9 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 2 | 1 | 39 | 0 | 22318 | 2 | 1 | 0 | 857 | 7 | 72 | 2 | 3 | 29878 | 3 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
10024 | 30037 | 225 | 0 | 0 | 0 | 0 | 0 | 0 | 5834 | 29475 | 174 | 10079 | 15 | 10056 | 14 | 11350 | 60 | 4289328 | 30306 | 30458 | 30415 | 28298 | 0 | 44 | 28916 | 11367 | 24 | 11354 | 24 | 11310 | 30461 | 30272 | 9 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 2 | 0 | 13605 | 4 | 0 | 0 | 849 | 3 | 97 | 3 | 5 | 29919 | 3 | 10000 | 10 | 30372 | 30453 | 30274 | 30514 | 30464 |
10024 | 30320 | 228 | 1 | 0 | 9 | 3 | 807 | 880 | 61 | 29547 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 4278512 | 30342 | 30417 | 30321 | 28313 | 0 | 10 | 28915 | 11214 | 24 | 11017 | 20 | 10972 | 30319 | 30368 | 6 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 1 | 0 | 0 | 2 | 0 | 0 | 829 | 2 | 72 | 3 | 2 | 29834 | 2 | 10000 | 10 | 30419 | 30414 | 30274 | 30465 | 30464 |
10024 | 30321 | 228 | 1 | 0 | 10 | 5 | 0 | 0 | 61 | 29547 | 25 | 10010 | 10 | 10008 | 12 | 10000 | 50 | 4277160 | 30270 | 30319 | 30367 | 28318 | 0 | 17 | 28916 | 10915 | 20 | 10325 | 20 | 11144 | 30178 | 30416 | 6 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 640 | 4 | 73 | 4 | 3 | 29736 | 2 | 10000 | 10 | 30466 | 30180 | 30463 | 30180 | 30180 |
10024 | 30452 | 227 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 29547 | 25 | 10026 | 12 | 10064 | 13 | 10750 | 81 | 4281216 | 30198 | 30370 | 30180 | 28315 | 0 | 11 | 28954 | 10614 | 20 | 10989 | 20 | 10978 | 30227 | 30509 | 8 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 29629 | 0 | 10000 | 10 | 30038 | 30038 | 30038 | 30038 | 30038 |
Count: 8
Code:
uqxtn h0, s8 uqxtn h1, s8 uqxtn h2, s8 uqxtn h3, s8 uqxtn h4, s8 uqxtn h5, s8 uqxtn h6, s8 uqxtn h7, s8
movi v8.16b, 9
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.2505
retire uop (01) | cycle (02) | 03 | 1f | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
80204 | 20058 | 150 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 1 | 20020 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80142 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
80204 | 20039 | 150 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 1 | 20020 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
80204 | 20039 | 150 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 1 | 20020 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
80204 | 20039 | 150 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 1 | 20020 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
80204 | 20039 | 150 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 0 | 20020 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 1 | 3 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
80204 | 20039 | 150 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 0 | 20020 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
80204 | 20039 | 150 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 1 | 20020 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
80204 | 20039 | 150 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 1 | 20020 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
80204 | 20039 | 150 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 1 | 20020 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
80204 | 20039 | 150 | 0 | 30 | 25 | 80108 | 100 | 80008 | 100 | 80020 | 500 | 640132 | 0 | 20020 | 20039 | 20039 | 9977 | 6 | 9990 | 80120 | 200 | 80032 | 200 | 80032 | 20039 | 20039 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 1 | 9 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 20036 | 80000 | 100 | 20040 | 20040 | 20040 | 20040 | 20040 |
Result (median cycles for code divided by count): 0.2505
retire uop (01) | cycle (02) | 03 | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
80024 | 20051 | 150 | 0 | 40 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 20020 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80000 | 20 | 80000 | 20039 | 20039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 4 | 9 | 5020 | 9 | 16 | 7 | 10 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |
80024 | 20039 | 150 | 0 | 40 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 20020 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80000 | 20 | 80000 | 20039 | 20039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 57 | 0 | 5020 | 10 | 16 | 10 | 7 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |
80024 | 20039 | 150 | 0 | 40 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 20020 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80000 | 20 | 80000 | 20039 | 20039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 0 | 5020 | 10 | 16 | 7 | 10 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |
80024 | 20039 | 150 | 0 | 40 | 25 | 80010 | 10 | 80097 | 10 | 80000 | 50 | 640000 | 20020 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80107 | 20 | 80000 | 20039 | 20039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 22 | 180 | 5020 | 8 | 16 | 7 | 10 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |
80024 | 20039 | 150 | 0 | 40 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 20020 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80000 | 20 | 80000 | 20039 | 20039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 24 | 0 | 5020 | 7 | 16 | 10 | 7 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |
80024 | 20039 | 150 | 0 | 40 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 20020 | 20039 | 20039 | 9996 | 3 | 10019 | 80010 | 20 | 80000 | 20 | 80000 | 20039 | 20039 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 1 | 3 | 5020 | 7 | 16 | 8 | 10 | 20036 | 80000 | 10 | 20040 | 20040 | 20040 | 20040 | 20040 |
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