Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UQXTN (S)

Test 1: uops

Code:

  uqxtn h0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372206125472510001000100039816003018303730372415328951000100010003037303711100110000373116112629100030383038303830383038
100430372206125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372308225472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723031225472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722039025472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110006073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  uqxtn h0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000000189295472510100100100001001000050042771600300183018130037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430084226000006901455295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000500071011611296330100001003003830038300383003830038
1020430037225000000061295478610100110100001031000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001001200071011611296330100001003003830038300383003830038
1020430037225000000061295478010100100100001001000050042771600300183003730037282643287451010020010000200100003003730037511020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011642296330100001003003830038300383003830038
10204300372250000000103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000100071011611296330100001003003830038300383003830038
1020430037225000000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500000001032954710010100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000300071011611296330100001003003830038300383003830038
1020430037225000000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000100071011611296330100001003003830038300383003830038
1020430037224000000061295472510100100100001001000050042771600300183003730131282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000006129547251001010100001010000504277160300183003730037282860262876710010201000020100003003730037111002110910101000010003090006402162229629010000103003830038300383003830038
1002430037225000000612954725100101010000101000050427716030018300373003728286032876710010201000020100003003730037111002110910101000010000030006402162229629010000103003830038300383003830038
1002430037225000000612954725100101010000101000050427716030018300373003728286032876710010201000020100003003730037111002110910101000010005000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160300183003730037282860328767100102010000201000030037300371110021109101010000100000150006402164329901110000103041330416301703041730416
1002430418228119839979251802954725100101010000101000050427851230018300373003728312042289151136424111412011306301773003711100211091010100001000452248130006402162229629010000103003830038300383003830038
1002430037225000000390529484177100791610056141105067428527230306304643017928317034289171106322113032410652304133041891100211091010100001021390223182108577722329878310000103003830038300383003830038
100243003722500000058342947517410079151005614113506042893283030630458304152829804428916113672411354241131030461302729110021109101010000100020136054008493973529919310000103037230453302743051430464
100243032022810938078806129547251001010100001010000504278512303423041730321283130102891511214241101720109723031930368611002110910101000010001002008292723229834210000103041930414302743046530464
100243032122810105006129547251001010100081210000504277160302703031930367283180172891610915201032520111443017830416611002110910101000010002000006404734329736210000103046630180304633018030180
10024304522270000006129547251002612100641310750814281216301983037030180283150112895410614201098920109783022730509811002110910101000010001000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  uqxtn h0, s8
  uqxtn h1, s8
  uqxtn h2, s8
  uqxtn h3, s8
  uqxtn h4, s8
  uqxtn h5, s8
  uqxtn h6, s8
  uqxtn h7, s8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815003025801081008000810080020500640132120020200392003999776999080120200800322008014220039200391180201100991001008000010000001115118016020036800001002004020040200402004020040
802042003915003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016020036800001002004020040200402004020040
802042003915003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016020036800001002004020040200402004020040
802042003915003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000101115118016020036800001002004020040200402004020040
802042003915003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000131115118016020036800001002004020040200402004020040
802042003915003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016020036800001002004020040200402004020040
802042003915003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016020036800001002004020040200402004020040
802042003915003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016020036800001002004020040200402004020040
802042003915003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016020036800001002004020040200402004020040
802042003915003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000191115118016020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001004950209167102003680000102004020040200402004020040
8002420039150040258001010800001080000506400002002020039200399996310019800102080000208000020039200391180021109101080000100570502010161072003680000102004020040200402004020040
800242003915004025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010000502010167102003680000102004020040200402004020040
80024200391500402580010108009710800005064000020020200392003999963100198001020801072080000200392003911800211091010800001002218050208167102003680000102004020040200402004020040
800242003915004025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010024050207161072003680000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001001350207168102003680000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000050207167102003680000102004020040200402004020040
800242003915004025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010000502012161292003680000102004020040200402004020040
80024200391500402580010108029110800005064000020020200392003999963100198001020800002080000200392003911800211091010800001002605020121612122003680000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001003205020101612122003680000102004020040200402004020040