Firestorm: URECPE (vector, 2S) measurements

Code:

  urecpe v0.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	124	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	24	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1056	3037	3037	1	1	1001	1000	3	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	24	0	124	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	24	0	159	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	0	105	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2919	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  urecpe v0.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	234	0	0	0	0	0	0	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	27	0	0	0	0	0	0	710	2	16	1	1	29919	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	0	0	0	89	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	0	0	0	0	710	1	16	1	1	29919	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	105	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	56	0	0	0	0	0	0	710	1	16	1	1	29919	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	0	0	0	225	19900	25	10100	100	10000	100	10000	500	1067451	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	0	0	0	0	710	1	16	1	1	29919	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	82	19900	25	10100	100	10000	100	10000	500	1067451	1	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	0	0	0	0	0	710	1	16	1	1	29919	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	0	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	1	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	2	0	0	0	0	0	0	710	1	16	1	1	29919	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	12	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	1	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	0	0	0	0	0	710	1	16	1	1	29919	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	1	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	0	0	0	0	710	1	16	1	1	29919	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	1	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	27	0	0	0	0	0	0	710	1	16	1	1	29919	0	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	1	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	2	0	0	0	0	0	0	710	1	16	1	1	29919	0	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	232	0	0	0	0	0	0	12	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	0	1	0	105	0	640	3	16	2	2	29919	0	10000	10	30085	30038	30038	30038	30038
10024	30037	232	0	0	0	0	0	0	33	0	195	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	12	0	104	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	3	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	0	0	0	0	12	0	104	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	2	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	242	0	0	0	0	0	0	12	0	103	19900	25	10010	11	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	3	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	15	0	124	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	36	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	241	0	0	0	0	0	0	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30084	28610	3	28799	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	1	0	0	385	19836	25	10010	10	10000	10	10042	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	4715	2	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	234	0	0	0	0	0	4	0	0	61	19900	25	10027	10	10000	10	10000	61	1067451	0	30090	30037	30037	28610	3	28893	10010	20	10000	20	10000	30037	30037	5	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	30065	0	10000	10	30228	30038	30038	30038	30038
10024	30037	242	0	0	0	1	0	0	3	0	61	19900	25	10010	12	10000	10	10000	50	1067612	0	30018	30037	30037	28610	3	28897	10010	20	10000	20	10000	30037	30037	5	1	10021	10	9	10	10	10000	10	0	0	0	2	0	3	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038

Test 3: throughput

Count: 8

Code:

  urecpe v0.2s, v8.2s
  urecpe v1.2s, v8.2s
  urecpe v2.2s, v8.2s
  urecpe v3.2s, v8.2s
  urecpe v4.2s, v8.2s
  urecpe v5.2s, v8.2s
  urecpe v6.2s, v8.2s
  urecpe v7.2s, v8.2s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80041	599	0	0	0	0	0	0	725	25	80100	100	80000	100	80000	500	640000	0	80020	0	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	80036	0	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	80020	0	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	80036	0	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	0	80020	0	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	80036	0	80000	100	80040	80040	80040	80040	80040
80205	80039	599	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	80020	0	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	80036	0	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	0	0	0	0	725	515	80652	100	80624	101	80702	500	644884	0	81088	0	81466	81122	70549	137	70966	80700	200	80881	200	80921	81423	81221	30	1	80201	100	99	100	100	80000	100	4	0	0	2	2	2	5334	1	23	2	1	80605	2	80000	100	80040	80040	80040	80040	80040
80204	80630	600	0	0	0	4	3063	1584	357	25	80100	100	80000	100	80000	500	640000	1	80020	0	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	80036	0	80000	100	80075	80040	80040	80040	80087
80204	80039	599	0	0	0	0	0	0	704	25	80100	100	80000	100	80000	500	640000	1	80020	0	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	80036	0	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	80020	0	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	80036	0	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	0	0	0	0	39	25	80100	100	80000	100	80000	500	640000	1	80020	0	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	6	1	1	1	5117	0	16	0	0	80036	0	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	0	0	0	0	704	25	80100	100	80000	100	80000	500	640000	1	80058	0	80039	80039	69971	6	69993	80100	200	80008	200	80048	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5117	0	16	0	0	80036	0	80000	100	80040	80040	80040	80040	80040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cd	cf	d0	d2	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80040	599	0	0	0	0	0	93	25	80010	10	80000	10	80000	50	640000	0	80020	0	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	16	16	0	0	16	13	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	0	2139	25	80010	10	80000	10	80000	50	640000	0	80020	0	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	6	0	5020	0	0	17	16	0	0	17	14	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	9	0	0	56	25	80010	10	80000	10	80000	50	640000	0	80020	0	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	13	16	2	0	13	15	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	80020	0	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	16	16	0	0	16	13	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	0	0	0	56	25	80010	10	80000	10	80000	50	640000	0	80020	0	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	17	16	0	0	14	17	80034	0	80000	10	80040	80040	80040	80040	80088
80024	80039	599	0	0	0	0	0	123	36	80010	10	80000	10	80000	50	640000	0	80020	0	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	1	0	0	0	5020	0	0	11	16	0	0	15	15	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	0	0	0	1790	25	80010	10	80000	10	80000	50	640000	0	80020	0	80088	80039	69986	3	70019	80010	20	80190	20	80000	80039	80039	2	1	80021	10	9	10	10	80000	10	0	4	0	0	0	5020	0	0	14	16	0	0	13	13	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	80020	0	80039	80039	69986	3	70019	80010	20	80000	20	80052	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	17	16	0	0	16	16	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	0	465	25	80010	10	80000	10	80000	50	640000	0	80020	0	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	3	15	16	0	0	15	12	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	80020	0	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	17	16	0	0	14	19	80034	0	80000	10	80040	80040	80040	80040	80040

URECPE (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations