Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

URECPE (vector, 2S)

Test 1: uops

Code:

  urecpe v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230124190025100010001000104451301830373037273832895100010001000303730371110011000073116112919100030383038303830383038
1004303723061190025100010001000104451301830373037273832895100010001000303730371110011000073116112919100030383038303830383038
1004303723061190025100010001000104451301830373037273832895100010001000303730371110011000073116112919100030383038303830383038
1004303723061190025100010001000104451301830373037273832895100010001000303730371110011000073116112919100030383038303830383038
1004303724061190025100010001000104451301830373037273832895100010001056303730371110011000373116112919100030383038303830383038
10043037240124190025100010001000104451301830373037273832895100010001000303730371110011000073116112919100030383038303830383038
10043037240159190025100010001000104451301830373037273832895100010001000303730371110011000073116112919100030383038303830383038
1004303723061190025100010001000104451301830373037273832895100010001000303730371110011000073116112919100030383038303830383038
1004303722061190025100010001000104451301830373037273832895100010001000303730371110011000073116112919100030383038303830383038
10043037230105190025100010001000104451301830373037273832895100010001000303730371110011000073116112919100030383038303830383038

Test 2: Latency 1->2

Code:

  urecpe v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372340000000061199002510100100100001001000050010674510300183003730037285883287451010020010000200100003003730037111020110099100100100001000027000000710216112991900100001003003830038300383003830038
1020430037232000000008919900251010010010000100100005001067451030018300373003728588328745101002001000020010000300373003711102011009910010010000100001000000710116112991900100001003003830038300383003830038
102043003723300000000105199002510100100100001001000050010674510300183003730037285883287451010020010000200100003003730037111020110099100100100001000056000000710116112991900100001003003830038300383003830038
10204300372320000000022519900251010010010000100100005001067451030018300373003728588328745101002001000020010000300373003711102011009910010010000100001000000710116112991900100001003003830038300383003830038
1020430037233000000008219900251010010010000100100005001067451130018300373003728588328745101002001000020010000300373003711102011009910010010000100003000000710116112991900100001003003830038300383003830038
1020430037232000000006119900251010010010000100100005001067451130018300373003728588328745101002001000020010000300373003711102011009910010010000100002000000710116112991900100001003003830038300383003830038
10204300372330000012006119900251010010010000100100005001067451130018300373003728588328745101002001000020010000300373003711102011009910010010000100003000000710116112991900100001003003830038300383003830038
1020430037233000000006119900251010010010000100100005001067451130018300373003728588328745101002001000020010000300373003711102011009910010010000100000030000710116112991900100001003003830038300383003830038
10204300372330000000061199002510100100100001001000050010674511300183003730037285883287451010020010000200100003003730037111020110099100100100001000027000000710116112991900100001003003830038300383003830038
1020430037233000000006119900251010010010000100100005001067451130018300373003728588328745101002001000020010000300373003711102011009910010010000100002000000710116112991900100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372320000001206119900251001010100001010000501067451030018300373003728610328767100102010000201000030037300371110021109101010000102001010506403162229919010000103008530038300383003830038
1002430037232000000330195199002510010101000010100005010674510300183003730037286103287671001020100002010000300373003711100211091010100001000010006402162229919010000103003830038300383003830038
1002430037233000000120104199002510010101000010100005010674510300183003730037286103287671001020100002010000300373003711100211091010100001000010306402162229919010000103003830038300383003830038
1002430037232000000120104199002510010101000010100005010674510300183003730037286103287671001020100002010000300373003711100211091010100001000020006402162229919010000103003830038300383003830038
1002430037242000000120103199002510010111000010100005010674510300183003730037286103287671001020100002010000300373003711100211091010100001000010306402162229919010000103003830038300383003830038
10024300372330000001501241990025100101010000101000050106745103001830037300372861032876710010201000020100003003730037111002110910101000010000103606402162229919010000103003830038300383003830038
10024300372410000000061199002510010101000010100005010674510300183003730084286103287991001020100002010000300373003711100211091010100001000000306402162229919010000103003830038300383003830038
100243003723300000100385198362510010101000010100425010674510300183003730037286103287671001020100002010000300373003711100211091010100001000010471526402162229919010000103003830038300383003830038
10024300372340000040061199002510027101000010100006110674510300903003730037286103288931001020100002010000300373003751100211091010100001000000006402162230065010000103022830038300383003830038
10024300372420001003061199002510010121000010100005010676120300183003730037286103288971001020100002010000300373003751100211091010100001000020306402162229919010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  urecpe v0.2s, v8.2s
  urecpe v1.2s, v8.2s
  urecpe v2.2s, v8.2s
  urecpe v3.2s, v8.2s
  urecpe v4.2s, v8.2s
  urecpe v5.2s, v8.2s
  urecpe v6.2s, v8.2s
  urecpe v7.2s, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020480041599000000725258010010080000100800005006400000800200800398003969971669993801002008000820080008800398003911802011009910010080000100000111511701600800360800001008004080040800408004080040
802048003959900000039258010010080000100800005006400000800200800398003969971669993801002008000820080008800398003911802011009910010080000100000111511701600800360800001008004080040800408004080040
802048003959900000039258010010080000100800005006400000800200800398003969971669993801002008000820080008800398003911802011009910010080000100000111511701600800360800001008004080040800408004080040
802058003959900000039258010010080000100800005006400001800200800398003969971669993801002008000820080008800398003911802011009910010080000100000111511701600800360800001008004080040800408004080040
80204800396000000007255158065210080624101807025006448840810880814668112270549137709668070020080881200809218142381221301802011009910010080000100400222533412321806052800001008004080040800408004080040
8020480630600000430631584357258010010080000100800005006400001800200800398003969971669993801002008000820080008800398003911802011009910010080000100000111511701600800360800001008007580040800408004080087
8020480039599000000704258010010080000100800005006400001800200800398003969971669993801002008000820080008800398003911802011009910010080000100000111511701600800360800001008004080040800408004080040
802048003960000000039258010010080000100800005006400001800200800398003969971669993801002008000820080008800398003911802011009910010080000100000111511701600800360800001008004080040800408004080040
802048003960000000039258010010080000100800005006400001800200800398003969971669993801002008000820080008800398003911802011009910010080000100006111511701600800360800001008004080040800408004080040
8020480039600000000704258010010080000100800005006400001800580800398003969971669993801002008000820080048800398003911802011009910010080000100000111511701600800360800001008004080040800408004080040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)0318191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accdcfd0d2d5map dispatch bubble (d6)d9daddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
800248004059900000932580010108000010800005064000008002008003980039699863700198001020800002080000800398003911800211091010800001000000502000161600161380034080000108004080040800408004080040
80024800395990000021392580010108000010800005064000008002008003980039699863700198001020800002080000800398003911800211091010800001000060502000171600171480034080000108004080040800408004080040
800248003960000900562580010108000010800005064000008002008003980039699863700198001020800002080000800398003911800211091010800001000000502000131620131580034080000108004080040800408004080040
800248003960000000502580010108000010800005064000008002008003980039699863700198001020800002080000800398003911800211091010800001000000502000161600161380034080000108004080040800408004080040
800248003960000000562580010108000010800005064000008002008003980039699863700198001020800002080000800398003911800211091010800001000000502000171600141780034080000108004080040800408004080088
8002480039599000001233680010108000010800005064000008002008003980039699863700198001020800002080000800398003911800211091010800001001000502000111600151580034080000108004080040800408004080040
80024800396000000017902580010108000010800005064000008002008008880039699863700198001020801902080000800398003921800211091010800001004000502000141600131380034080000108004080040800408004080040
800248003960000000502580010108000010800005064000008002008003980039699863700198001020800002080052800398003911800211091010800001000000502000171600161680034080000108004080040800408004080040
8002480039599000004652580010108000010800005064000008002008003980039699863700198001020800002080000800398003911800211091010800001000000502003151600151280034080000108004080040800408004080040
800248003959900000502580010108000010800005064000008002008003980039699863700198001020800002080000800398003911800211091010800001000000502000171600141980034080000108004080040800408004080040