Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

URHADD (vector, 8B)

Test 1: uops

Code:

  urhadd v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371600611687251000100010002646800201820372037157231895100010002000203720371110011000073116121787100020382038203820382038
100420371500611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371600611687251000100010002646800201820372037157231895100010002000203720371110011000073216121785100020382038203820382038
1004203715112611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715115611687251000100010002646800201820372037157131895100010002000203720371110011000073116211787100020382038203820382038
100420371500901687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715012611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500681687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646800201820372037157131895100010002000203720371110011000073116111787100020382038203820382038
1004203715015611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  urhadd v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102161119791100001002003820038200382003820038
102042003715000606119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150000016819687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500035706119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100107101161119791100001002003820038200382003820038
10204200371500018053619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150002106119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006025219687251010010410000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150001506119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150001806119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001006403163319785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001006403163319785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001022100002020000200372003711100211091010100001006403163319785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001006403163319785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001006403163319785010000102003820038200382003820038
100242003715000396119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001006403163319785010000102003820038200382003820038
10024200371490006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001006403163319785010000102003820038200382003820038
1002420037150004536119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001006403163319785010000102003820038200382003820038
1002420037150002410319687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001036403163319785010000102008620084200382003820086
1002420037150002586119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001036403163319785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  urhadd v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150118611968725101001001000010010000500284768020018200372013318422071874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715010611968725101001001000010010000626284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010010071011611197910100001002003820038200382003820038
1020420037150107261968725101001251000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000171011611197910100001002003820038200382003820038
1020420037150007261968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500321611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968725101001251000012510000500284768020018200372003718422031874410100200100002002000020037200371110201100991001001000010000071011631197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000003300611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037150000001500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037150000003600611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037150000003900611968725100221010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037150000001500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820085
100242003715000000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037150000000001891968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000900611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002210910101000010000000006402162219785010000102003820038200382003820038
1002420037150000001500611968725100101010000101000050284768002001820037200371844831876710010201000020200002003720037111002110910101000010000000006402244219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  urhadd v0.8b, v8.8b, v9.8b
  urhadd v1.8b, v8.8b, v9.8b
  urhadd v2.8b, v8.8b, v9.8b
  urhadd v3.8b, v8.8b, v9.8b
  urhadd v4.8b, v8.8b, v9.8b
  urhadd v5.8b, v8.8b, v9.8b
  urhadd v6.8b, v8.8b, v9.8b
  urhadd v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0309l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420057150000003604025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511041623200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511031623200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000020098200382003899733999680100200800002001600002003820038118020110099100100800001000000000511021633200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511031632200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511031623200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511031623200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511031633200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511041632200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511031632200350800001002003920039200392003920039
802042003815000000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511031623200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)dbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420047150039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502081607720035080000102003920039200392008920039
8002420038150039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502081607720035080000102003920039200392003920039
8002420038150039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502071607720035080000102003920039200392003920039
8002420038150039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502081607720035080000102003920039200392003920039
80024200381502439258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502071607720035080000102003920039200392003920039
80024200381500392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100005020101606720035080000102003920039200392003920039
8002420038150039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502071607620035080000102003920039200392003920039
8002420038150039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502071607720035080000102003920039200392003920039
8002420038150039258008710800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502061605720035080000102003920039200392003920039
8002420038150039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000502071607520035080000102003920039200392003920039