Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

URSHL (vector, 2D)

Test 1: uops

Code:

  urshl v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037220251254825100010001000398313130183037303724153289510001000200030373037111001100002173116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100003073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723072225482510001000100039831303018303730372415328951000100020003037303711100110000973116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110002073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  urshl v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
10204300372250000000612954825101001031000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
10204300372240000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020220000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
10204300372240000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071021622296340100001003003830038300383003830038
102043003722500000006129548251010010010000100100005004277313300183003730037282653287451010020010000200200003008430037111020110099100100100001000000000710216222963427100001003032730324303723032530323

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243065323711141317161232157392943129510095161011218117887142895260304863051330461283354629009115072411152202228830320300371110021109101010000102048270116401162229668210000103003830038300383021430038
10024300372390000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372240000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000221206402162229630010000103003830038300383003830038
10024300372250000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
100243003722400000005230294851041008015100721211192724289225030342304643022528305212893611357221049320227703027030463811002110910101000010000306402162229630310000103045430274304093018030262
100243008422801482677041201429512198100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010222821807441803229702110000103036730464302293046030464
10024304132280100000103295482510010101000010100005042773130300543003730037282961128786100102010000202000030037300371110021109101010000100001104806402162229630010000103003830038300383008530133

Test 3: Latency 1->3

Code:

  urshl v0.2d, v1.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
102043008622600000001032954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731330018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003008530132301333013430038
102043008522510000006129530251010010010000100100005004277313300183008430037282653287451010020010000200200003003730037111020110099100100100001000020255654738232122970315100001003013330132301343013530135

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722406129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250285829548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722506129548251001010100001010000504277313300183003730037282870328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  urshl v0.2d, v8.2d, v9.2d
  urshl v1.2d, v8.2d, v9.2d
  urshl v2.2d, v8.2d, v9.2d
  urshl v3.2d, v8.2d, v9.2d
  urshl v4.2d, v8.2d, v9.2d
  urshl v5.2d, v8.2d, v9.2d
  urshl v6.2d, v8.2d, v9.2d
  urshl v7.2d, v8.2d, v9.2d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004815000025525801001008000010080000500640000200200200392003999733999780100200800002001600002003920039118020110099100100800001000651103163320087800001002004020040200402004020040
80204200391500004125801001008000010080000500640000200200200392003999733999780100200800002001600002003920039118020110099100100800001000051103163220036800001002004020040200402004020040
80204200391500004125801001008000010080000500640000200200200392003999733999780100200800002001600002003920039118020110099100100800001000051102163220036800001002004020040200402004020040
80204200391500004125801001008000010080000500640000200200200392003999733999780100200800002001600002003920039118020110099100100800001000051103163320036800001002004020040200402004020040
80204200391500008325801001008000010080000500640000200200200392003999733999780100200800002001600002003920039118020110099100100800001000051103164220036800001002004020040200402004020040
80204200391500004125801001008000010080000500640000200200200392003999733999780100200800002001600002003920039118020110099100100800001000051103162320036800001002004020040200402004020040
80204200391500004125801001008000010080000500640000200200200392003999733999780100200800002001600002003920039118020110099100100800001000051103163320036800001002004020040200402004020040
802042003915000013125801001008000010080000500640000200200200392003999733999780100200800002001600002003920039118020110099100100800001000051103162320036800001002004020040200402004020040
802042003915000032625801001008000010080000500640000200200200392003999733999780100200800002001600002003920039118020110099100100800001000051103163320036800001002004020040200402004020040
802042003915000010825801001008000010080000500640000200200200392003999733999780100200800002001600002003920039118020110099100100800001000051102162320036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000005020051657200362380000102004020040200402004020040
8002420039150000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000005020051657200362380000102004020040200402004020040
8002420039150000040258001010800001080000506400000200202008920039999631001980010208000020160000200392003911800211091010800001000005020061665200362780000102004020040200402004020040
80024200391500000402580010108000010800005064000002002020039200399996310019800102080000201600002003920039118002110910108000010006005020071677200362180000102004020040200402004020040
80024200391500000242258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000305020071674200362380000102004020040200402004020040
8002420039150000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000005020071675200362180000102004020040200402004020040
8002420039150000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000005020071656200362180000102004020040200402004020040
800242003915000003780258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001005005020051674200362380000102004020040200402004020040
80024200391500000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010005705020041674200362180000102004020040200402004020040
8002420039150000063258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000005020051665200362780000102004020040200402004020040