Firestorm: URSHL (vector, 8B) measurements

Code:

  urshl v0.8b, v0.8b, v1.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	186	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	27	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	27	61	2539	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	179	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  urshl v0.8b, v0.8b, v1.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	57	441	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28272	6	28741	10100	200	10008	200	20362	30085	30037	1	1	10201	100	99	0	100	100	10000	100	2	3	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	30	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28272	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	3	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	45	61	29548	25	10100	100	10000	100	10000	542	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	33	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	6	5547	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29706	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	1	270	84	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	45	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	6	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	10	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	57	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	18	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	0	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	477	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	82	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30078	225	0	0	0	0	69	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	417	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	405	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30085	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	417	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	396	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	30034	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->3

Code:

  urshl v0.8b, v1.8b, v0.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30088	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	626	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	3	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	202	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	25	10000	100	30038	30038	30038	30038	30077
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29548	25	10100	100	10007	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	237	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	4	4	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	3	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	4	4	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	4	4	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	4	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	4	4	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	6	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	4	4	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	21	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	4	4	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	54	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	4	4	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	4	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	4	16	4	4	29630	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  urshl v0.8b, v8.8b, v9.8b
  urshl v1.8b, v8.8b, v9.8b
  urshl v2.8b, v8.8b, v9.8b
  urshl v3.8b, v8.8b, v9.8b
  urshl v4.8b, v8.8b, v9.8b
  urshl v5.8b, v8.8b, v9.8b
  urshl v6.8b, v8.8b, v9.8b
  urshl v7.8b, v8.8b, v9.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20039	150	0	0	0	0	15	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	2	0	0	0	1	1	1	5118	0	16	0	0	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	41	25	80100	100	80000	100	80000	500	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	41	25	80100	100	80000	100	80000	500	640000	1	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	41	25	80100	100	80000	100	80000	500	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	2	0	171	0	0	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	41	25	80100	100	80000	100	80000	500	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	706	25	80100	100	80000	100	80000	500	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	4	0	0	0	0	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	41	25	80100	100	80000	100	80000	500	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	41	25	80100	100	80000	100	80000	500	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	0	0	0	0	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	41	25	80100	100	80000	100	80000	500	640000	1	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	7	0	0	0	0	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	706	25	80100	100	80000	100	80000	500	640000	0	20020	20039	20039	9973	3	9997	80100	200	80000	200	160000	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	0	0	0	5110	1	16	1	1	20036	0	80000	100	20040	20040	20040	20040	20040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	3	16	2	3	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	50	25	80010	10	80000	10	80000	50	640000	1	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	3	16	3	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	2	0	0	5020	2	16	2	3	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	1	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	10	0	0	5020	3	16	3	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	1	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	4	0	0	5020	3	16	3	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	1	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	3	16	4	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	1	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	3	16	3	3	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	1	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	1	3	0	5020	3	16	3	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	0	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	2	0	0	3	0	5020	3	16	3	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	40	25	80010	10	80000	10	80000	50	640000	1	20020	0	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	3	16	2	3	20036	80000	10	20040	20040	20040	20040	20040

URSHL (vector, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations