Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

URSHR (vector, 16B)

Test 1: uops

Code:

  urshr v0.16b, v0.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372206125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723015625472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722156125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723486125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372366125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372266125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  urshr v0.16b, v0.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
1020430037225636612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010020007101161229633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010020007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722510100000267295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000000644101651029629010000103003830038300383003830038
1002430037225101000002672954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006441016111029629010000103003830038300383003830038
100243003722410100000267295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000000644616101029629010000103003830038300383003830038
100243003722510100001322672954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006441016101029629010000103003830038300383003830038
10024300372251010000026729547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000001506441016101029629010000103003830038300383003830038
10024300372251010000026540295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000000644111681029629010000103003830038300383003830038
1002430037225101000002672954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006441016101029629010000103003830038300383003830038
100243003722510100030267295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000000644111611629629010000103003830038300383003830038
100243003722510100100267295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000000644816101029629010000103003830038300383003830038
1002430037225101000002672954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006441117101129629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  urshr v0.16b, v8.16b, #3
  urshr v1.16b, v8.16b, #3
  urshr v2.16b, v8.16b, #3
  urshr v3.16b, v8.16b, #3
  urshr v4.16b, v8.16b, #3
  urshr v5.16b, v8.16b, #3
  urshr v6.16b, v8.16b, #3
  urshr v7.16b, v8.16b, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391500762580108100800081008002050064013200200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511801360120036800001002004020040200402004020040
80204200391500302580108100800081008002050064013200200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511800160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013200200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511800160020036800001002004020040200402004020040
80204200391500512580108100800081008002050064013200200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511800160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013200200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511800160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013200200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511800160020036800001002004020040200402004020040
802042003915001602580108100800081008002050064013200200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511800160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013200200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511800160120036800001002004020040200402004020040
802042003915009392580108100800081008002050064013200200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511800160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013200200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511800160120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015000402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003600080000102004020040200402004020040
800242003915000402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003600080000102004020040200402004020040
8002420039155001242580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003600080000102004020040200402004020040
800242003915000402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010605020116112003600080000102004020040200402004020040
800242003915000402580010108000010800005564000000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003600080000102004020040200402004020040
800242003915000402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003600080000102004020040200402004020040
800242003915000402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003600080000102004020040200402004020040
800242003915000402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003600080000102004020040200402004020040
8002420039150004025800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100050201161120036042080000102004020040200402004020040
800242003915000402580010108000010801075064000000200202003920039999631001980010208000020800002003920039118002110910108000010105020116112003600080000102004020040200402004020040