Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

URSHR (vector, 2D)

Test 1: uops

Code:

  urshr v0.2d, v0.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)030b1e3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
1004303723006425472510001000100039816013018303730372414328951000100010003037303711100110000073316332629100030383038303830383038
1004303722006125472510001000100039816013018303730372414328951000100010003037303711100110000073316332629100030383038303830383086
1004303722006125472510001000100039816013018303730372414328951000100010003037303711100110000073316332629100030383038303830383038
10043037230061254725100010001000398160130183037303724143289510001000100030373037111001100034373316332629100030383038303830383038
1004303722006125472510001000100039816013018303730372414328951000100010003037303711100110000073316332629100030383038303830383038
10043037220061254725100010001000398160130183037303724143289510001000100030373037111001100035373216332629100030383038303830383038
10043037230156125472510001000100039816013018303730372414328951000100010003037303711100110000073316332629100030383038303830383038
1004303723006125472510001000100039816013018303730372414328951000100010003037303711100110000073316332629100030383038303830383038
1004303722008225472510001000100039816013018303730372414328951000100010003037303711100110000073316332629100030383038303830383038
10043037230061254725100010001000398160130183037303724143289510001000100030373037111001100022073216332629100030383038303830383038

Test 2: Latency 1->2

Code:

  urshr v0.2d, v0.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)030818191e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8a9acc5branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1020430037224000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000171011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001001000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287651010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000361295472510100100100001211000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037224000061295472510100100100001001000062642771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383008130038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
10204300372250009168295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)03080b18191e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a7a8a9acc2c5cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10024300372261000144061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000000064021622296290010000103003830038300383003830038
10024300372250000540103295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000000064021622297010010000103003830038300383003830038
100243003722400000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000000064021622296290010000103003830038300383003830038
1002430037225000036061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000000064021622296290010000103003830038300383003830038
1002430037225000036061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000000064021622296290010000103003830038300383003830038
1002430037224100008861295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000000064021622296290010000103003830038300383003830038
100243003722500005406129547251001010100081110000504280127030270303673038728305332889911064221097822109793036830324811002110910101000010221102205820078857243299433010000103041830415303563037030367
10024304022281077939616457429484157100791110048151090060428662403009030369303682831127288961114020113182011143303673036791100211091010100001000000000064021644298094010000103036830371303673040530086
100243036822801878164402613294841591006914100561411050654285952030270303693037028309342886311212261114124109773037230367911002110910101000010021121685000079334133299534010000103046530463304663046330464
1002430460228109979570458392946617010088161003217113057142879760303063046430414283124128935115122412442201194230605305071211002110910101000010200143019520074646452296290010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  urshr v0.2d, v8.2d, #3
  urshr v1.2d, v8.2d, #3
  urshr v2.2d, v8.2d, #3
  urshr v3.2d, v8.2d, #3
  urshr v4.2d, v8.2d, #3
  urshr v5.2d, v8.2d, #3
  urshr v6.2d, v8.2d, #3
  urshr v7.2d, v8.2d, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)0308191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8acc5branch mispredict (cb)cdcfd5d6e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
80204200611500027302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040
8020420039150000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040
8020420039150000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040
8020420039150100302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001002000111511801620036800001002004020040200402004020040
8020420039150000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040
8020420039150000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040
8020420039150000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040
8020420039150000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040
80204200391500003025801081008000810080020500640132120020200392003910006699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040
8020420039150000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)03080b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc2cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
8002420039150000000402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020516552003680000102004020040200402004020040
8002420039150000000402580010108000010800005064000020020200392003999963100198001020800002080314200392003911800211091010800001000300025020516442003680000102004020040200402004020040
8002420039150000000402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020416442003680000102004020040200402004020040
8002420039150000000402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000010305020539552003680000102004020040200402004020040
800242003915011001440402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020316442003680000102004020040200402004020040
8002420039150000000402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020316432003680000102004020040200402004020040
80024200391500000005152580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020516342003680000102004020040200402004020040
8002420039150000000402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020416442003680000102004020040200402004020040
8002420039150000000402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020516442003680000102004020040200402004020040
8002420039150000000402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000000005020516552003680000102004020040200402004020040