Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

URSHR (vector, 8B)

Test 1: uops

Code:

  urshr v0.8b, v0.8b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)030b18191e3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a0a8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
100430372200006125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372200006125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303722000010325472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372300006125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372300006125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372300096125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372300006125472510001000100039816030183037303724143289510001000100030373037111001100000373116112629100030383038303830383071
100430372300006125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372200038425472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723000246125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  urshr v0.8b, v0.8b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)031e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9facbranch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
102043003722506129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
1020430037225061295472510100100100001001000050042771603001830037300372826427287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)030708090a0b18191e1f3a3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc2cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
100243003722500000005100612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000000006404164329629010000103003830038300383003830038
100243003722500000003300612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000000006404163429629010000103003830038300383003830038
100243003722500000004800612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000000006404164329629010000103003830038300383003830038
100243003722400000000002512954725100101010000101000050427716030018300373003728286328767100102010162201000030037300371110021109101010000100000000006404163429629010000103003830038300383003830038
100243003722500000004200612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000000006404163429629010000103003830038300383003830038
1002430037225000000030006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000000012006404163429629010000103003830038300383003830038
10024300372250000000300612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000000006403164329629010000103003830038300383003830038
1002430037225000000042001032954725100101010000101000050427716030018300373003728286328767100102010000201000030180300371110021109101010000100000000006404164429629010000103003830038300383003830038
100243003722500000001500612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000000006404163429629010000103003830038300383003830038
10024300372250000056924616045182948415410038121004816109006142866243027030322304052831412288991121520111432211153303683032291100211091010100001044210018193207467814429881410000103037230358303703036830415

Test 3: throughput

Count: 8

Code:

  urshr v0.8b, v8.8b, #3
  urshr v1.8b, v8.8b, #3
  urshr v2.8b, v8.8b, #3
  urshr v3.8b, v8.8b, #3
  urshr v4.8b, v8.8b, #3
  urshr v5.8b, v8.8b, #3
  urshr v6.8b, v8.8b, #3
  urshr v7.8b, v8.8b, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)0318191e203f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
8020420061150000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
8020420039150000030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a7a8acbranch mispredict (cb)cfd0d5d6dbddinst fetch restart (de)e0eb? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
800242003915004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001001612050200416044200362180000102004020040200402004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000005020061604620036080000102004020040200402004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000305020031607720036080000102004020040200402004020040
8002420039150040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000005020061606620036080000102004020040200402004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000005020071604420036080000102004020040200402004020040
8002420039150040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000005020031603420036080000102004020040200402004020040
8002420039150040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000005020061604420036080000102004020040200402004020040
8002420039150040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000005020071604320036080000102004020040200402004020040
8002420039150040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000005020031604720036080000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999963100198001020801052080000200392003911800211091010800001020047305020061604420036080000102004020040200402004020040