Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

URSQRTE (vector, 2S)

Test 1: uops

Code:

  ursqrte v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)0304191e3a3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a6a8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
100430372200026219002510001000100010445130183037303727383289510001000100030373037111001100000076416442919100030383038303830383038
100430372310026219002510001000100010445130183037303727383289510001000100030373037111001100000076416442919100030383038303830383038
100430372210026219002510001000100010445130183037303727383289510001000100030373037111001100000076416442919100030383038303830383038
100430372310026219002510001000100010461230183037303727383289510001000100030373037111001100000076416442919100030853038303830383038
100430372310026219002510001000100010445130183037303727383289510001000100030373037111001100000076416442919100030383038303830383038
1004303722100215719002510001000100010445130183037303727383289510001000100030373037111001100000076416442919100030383038303830383038
100430372310026219002510001000100010445130183037303727383289510001000100030373037111001100000076416442919100030383038303830383038
100430372310026219002510001000100010445130183037303727383289510001000100030373037111001100000076416442919100030383038303830383038
100430372310026219002510001000100010445130183037303727383289510001000100030373037111001100001076416442919100030383038303830383038
1004303723100246119002510001000100010445130183037303727383289510001000100030373037111001100000076416442919100030383038303830383038

Test 2: Latency 1->2

Code:

  ursqrte v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)0304080b18191e1f3a3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)6061696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8acc2cfd0d2d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204300372330000000061199002510100100100081001000050010674510030018300373003728588328745101002001000020010000300373003711102011009910010010000100000007100021622299190100001003003830038300383003830038
10204300372330000000061199002510100100100001001000050010674510030018300373003728588328745101002001000020010000300373003711102011009910010010000100000007100021622299190100001003003830038300383003830038
10204300372330000000061199002510100100100001001000050010674510030018300373003728588328745101002001000020010000300373003711102011009910010010000100000007100021622299190100001003003830038300383003830038
10204300372320000000061199002510100100100001001000050010674510030018300373003728588328745101002001000020010000300373003711102011009910010010000100000007100021622299190100001003003830038300383003830038
10204300372330000000061199002510100100100001001000050010674510030018300373003728588328745101002001000020010000300373003711102011009910010010000100000007100021622299190100001003003830038300383003830038
10204300372320000000061199002510100100100001001000050010674510030018300373003728588328745101002001000020010000300373003711102011009910010010000100000007100021622299190100001003003830038300383003830038
10204300372330000000061199002510100100100001001000050010674510030018300373003728588328745101002001000020010000300373003711102011009910010010000100000007100021622299190100001003003830038300383003830038
10204300372330000000061199002510100100100001001000050010674510030018300373003728588328745101002001000020010000300373003711102011009910010010000100000007100021622299190100001003003830038300383003830038
10204300372330000000089199002510100100100001001000050010674510030018300373003728588328745101002001000020010000300373003711102011009910010010000100000007100021622299190100001003003830038300383003830038
1020430037242000002400061199002510100100100001001000050010674510030018300373003728588328745101002001000020010000300373003711102011009910010010000100000007100021622299190100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)030e1e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10024300372320061199002510010101000010100005010674511300183003730037286103287671001020100002010000300373003711100211091010100001000006402162229919010000103003830038300383003830038
10024300372330061199002510010101000010100005010674511300183003730037286103287671001020100002010000300373003711100211091010100001000006402162229919010000103003830038300383003830038
10024300372330061199002510010101000010100005010674511300183003730037286103287671001020100002010000300373003711100211091010100001000036402162229919010000103003830038300383003830038
10024300372330061199002510010101000010100005010674511300183003730037286103287671001020100002010000300373003711100211091010100001020006402162229919010000103003830038300383003830038
100243003723201261199002510010101000010100005010674511300183003730037286103287671001020100002010000300373003711100211091010100001000006402162229919010000103003830038300383003830038
10024300372330061199002510010101000010100005010674511300183003730037286103287891001020100002010000300373003711100211091010100001000006402162229919010000103003830038300383003830038
10024300372330061199002510010101000010100005010674511300183003730037286123287671001020100002010000300373003711100211091010100001000036402162229919010000103003830038300383003830038
10024300372330061199002510010101000010100005010674510300183003730037286103287671001020100002010000300373003711100211091010100001000006402162229919010000103003830038300383003830038
10024300372330061199002510010101000010100005010674510300183003730037286103287671001020100002010000300373003711100211091010100001000106402162229919010000103003830038300383003830038
10024300372330061199002510010101000010100425010674510300183003730037286103287671001020100002010000300373003711100211091010100001000006402162229919010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  ursqrte v0.2s, v8.2s
  ursqrte v1.2s, v8.2s
  ursqrte v2.2s, v8.2s
  ursqrte v3.2s, v8.2s
  ursqrte v4.2s, v8.2s
  ursqrte v5.2s, v8.2s
  ursqrte v6.2s, v8.2s
  ursqrte v7.2s, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire (01)cycle (02)03081e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8a9acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
802048004059900083625801001008000010080000500640000180020800398003969971669993801002008000820080008800398003911802011009910010080000100000011151170160080036800001008004080040800408004080040
802048003960000062625801001008000010080000500640000080020800398003969971669993801002008000820080008800398003911802011009910010080000100000011151170160080036800001008004080040800408004080040
802048003959900029325801001008000010080000500640000080020800398003969971669993801002008000820080008800398003911802011009910010080000100000011151170160080036800001008004080040800408004080040
8020480039599000487258010010080000100800005006400001800208003980039699716699938010020080008200800088003980039118020110099100100800001005600011151170160080036800001008004080040800408004080040
802048013759900021125801001008000010080000500640000080020800398003969971669993801002008000820080008800398003911802011009910010080000100000011151170160080036800001008004080040800408004080040
802048003960000039125801001008000010080000500640000180020800398003969971669993801002008000820080008800398003911802011009910010080000100000011151170160080036800001008004080040800408004080040
802048003959910050725801001008000010080000500640000180020800398003969971669993801002008000820080008800398003911802011009910010080000100000011151170160080036800001008004080040800408004080040
802048003959900049325801001008000010080000500640000080020800888003969971669993801352008000820080008800398003911802011009910010080000100000011151170160080036800001008004080040800408004080040
802048003960000040625801001008000010080000500640000180069800398003969971669993801002008000820080008800398003911802011009910010080000100000011151170160080036800001008004080040800408004080040
802048003960000038525801001008000010080000500640000080020800398003969971669993801002008000820080008800398003911802011009910010080000100000011151170160080036800001008004080040800408004080040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire (01)cycle (02)030b181e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8acc2c5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
800248004059900007152580010108000010800005064000001800208003980039699863700198001020800002080000800398003911800211091010800001000000050204163380034080000108004080040800408004080040
80024800395990000502580010108000010800005064000001800208003980039699863700198001020800002080000800398003911800211091010800001000000050209164380034080000108004080040800408004080040
80024800396000000502580010108000010800005064000001800208003980039699863700198001020800002080000800398003911800211091010800001000000050205165580034080000108004080040802378004080040
80024800396000000502580010108000010800005064000001800208003980039699863700198003220800002080000800398003911800211091010800001000600050205165580034080000108004080040800408004080236
80024800396000000502580010108000010800005064000001800208003980039699863700198001020800002080000800398003911800211091010800001000000050204165480034080000108004080040800408004080040
800248003959900001342580058108000010800005064000001800208003980039699863700198001020800002080000800398003911800211091010800001000100050204163380034080000108004080040800408004080040
80024800395990000502580010108000010800265064000001800208003980039699863700198001020800002080000800398003911800211091010800001000000050205164380034080000108004080040800408018880040
8002480039600025520502580010108000010800005064000001800208003980039699863700198001020800002080000800398003911800211091010800001000030150203163380034080000108004080040800408004080040
80024800395990000502580010108000010800005064000001800208003980039699863700198001020800002080000800398003911800211091010800001000000050207164580034080000108004080040800408004080040
80024800396000060715258001010800001080000506400000180020800398003969986197001980010208000020800008003980039118002110910108000010000150050204163380034080000108004080040800408004080090