Firestorm: URSQRTE (vector, 2S) measurements

Code:

  ursqrte v0.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	19	1e	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	0	0	2	62	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	76	4	16	4	4	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	1	0	0	2	62	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	76	4	16	4	4	2919	1000	3038	3038	3038	3038	3038
1004	3037	22	1	0	0	2	62	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	76	4	16	4	4	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	1	0	0	2	62	1900	25	1000	1000	1000	104612	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	76	4	16	4	4	2919	1000	3085	3038	3038	3038	3038
1004	3037	23	1	0	0	2	62	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	76	4	16	4	4	2919	1000	3038	3038	3038	3038	3038
1004	3037	22	1	0	0	2	157	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	76	4	16	4	4	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	1	0	0	2	62	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	76	4	16	4	4	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	1	0	0	2	62	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	76	4	16	4	4	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	1	0	0	2	62	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	1	0	76	4	16	4	4	2919	1000	3038	3038	3038	3038	3038
1004	3037	23	1	0	0	2	461	1900	25	1000	1000	1000	104451	3018	3037	3037	2738	3	2895	1000	1000	1000	3037	3037	1	1	1001	1000	0	0	0	76	4	16	4	4	2919	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  ursqrte v0.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	233	0	0	0	0	0	0	0	0	61	19900	25	10100	100	10008	100	10000	500	1067451	0	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	0	2	16	2	2	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	0	2	16	2	2	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	0	2	16	2	2	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	0	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	0	2	16	2	2	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	0	2	16	2	2	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	0	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	0	2	16	2	2	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	0	2	16	2	2	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	0	2	16	2	2	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	0	89	19900	25	10100	100	10000	100	10000	500	1067451	0	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	0	2	16	2	2	29919	0	10000	100	30038	30038	30038	30038	30038
10204	30037	242	0	0	0	0	0	240	0	0	61	19900	25	10100	100	10000	100	10000	500	1067451	0	0	30018	30037	30037	28588	3	28745	10100	200	10000	200	10000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	0	0	2	16	2	2	29919	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	232	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	12	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28610	3	28789	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	1	30018	30037	30037	28612	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	19900	25	10010	10	10000	10	10000	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	19900	25	10010	10	10000	10	10042	50	1067451	0	30018	30037	30037	28610	3	28767	10010	20	10000	20	10000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29919	0	10000	10	30038	30038	30038	30038	30038

Test 3: throughput

Count: 8

Code:

  ursqrte v0.2s, v8.2s
  ursqrte v1.2s, v8.2s
  ursqrte v2.2s, v8.2s
  ursqrte v3.2s, v8.2s
  ursqrte v4.2s, v8.2s
  ursqrte v5.2s, v8.2s
  ursqrte v6.2s, v8.2s
  ursqrte v7.2s, v8.2s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80040	599	0	0	0	836	25	80100	100	80000	100	80000	500	640000	1	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	0	626	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	0	293	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	0	487	25	80100	100	80000	100	80000	500	640000	1	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	56	0	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80137	599	0	0	0	211	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	0	391	25	80100	100	80000	100	80000	500	640000	1	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	599	1	0	0	507	25	80100	100	80000	100	80000	500	640000	1	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	599	0	0	0	493	25	80100	100	80000	100	80000	500	640000	0	80020	80088	80039	69971	6	69993	80135	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	0	406	25	80100	100	80000	100	80000	500	640000	1	80069	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040
80204	80039	600	0	0	0	385	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	69971	6	69993	80100	200	80008	200	80008	80039	80039	1	1	80201	100	99	100	100	80000	100	0	0	0	0	1	1	1	5117	0	16	0	0	80036	80000	100	80040	80040	80040	80040	80040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80040	599	0	0	0	0	715	25	80010	10	80000	10	80000	50	640000	0	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	4	16	3	3	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	9	16	4	3	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	5	16	5	5	80034	0	80000	10	80040	80040	80237	80040	80040
80024	80039	600	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	1	80020	80039	80039	69986	3	70019	80032	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	6	0	0	0	5020	5	16	5	5	80034	0	80000	10	80040	80040	80040	80040	80236
80024	80039	600	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	4	16	5	4	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	134	25	80058	10	80000	10	80000	50	640000	0	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	1	0	0	0	5020	4	16	3	3	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	50	25	80010	10	80000	10	80026	50	640000	0	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	5	16	4	3	80034	0	80000	10	80040	80040	80040	80188	80040
80024	80039	600	0	2	552	0	50	25	80010	10	80000	10	80000	50	640000	0	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	3	0	1	5020	3	16	3	3	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	599	0	0	0	0	50	25	80010	10	80000	10	80000	50	640000	0	1	80020	80039	80039	69986	3	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5020	7	16	4	5	80034	0	80000	10	80040	80040	80040	80040	80040
80024	80039	600	0	0	6	0	715	25	80010	10	80000	10	80000	50	640000	0	1	80020	80039	80039	69986	19	70019	80010	20	80000	20	80000	80039	80039	1	1	80021	10	9	10	10	80000	10	0	0	0	15	0	0	5020	4	16	3	3	80034	0	80000	10	80040	80040	80040	80040	80090

URSQRTE (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations