Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

URSQRTE (vector, 4S)

Test 1: uops

Code:

  ursqrte v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037240061190025100010001000104451130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038
10043037240061190025100010001000104451130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038
10043037230061190025100010001000104451130183037303727383289510001000100030373037111001100000073116112919100030383038308530383038
100430372308861190025100010001000104451130183037303727383289510001056100030373037111001100000073124112919100030383038303830383038
1004303723003091900251008100010001044511301830373037273832895100010001000303730371110011000001873116112919100030383038303830383038
100430372300103190025100010001000104451130183037303727383289510001000100030373037111001100001073116112919100030383038303830383038
10043037230098190025100010001000104451130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038
10043037230061190025100010001000104451130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038
100430372300247190025100010001000104451130183037303727383289510001000100030373037111001100001073116112919100030383038303830383038
10043037230061190025100010001000104451130183037303727383289510001000100030373037111001100000073116112919100030383038303830383038

Test 2: Latency 1->2

Code:

  ursqrte v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723300000611990025101001001000010010000500106745113001830037300372858832874510100200100002001000030037300371110201100991001001000010000071011611299190100001003003830038300383003830038
102043003723300000611990025101001001000010010000500106745103001830037300372858832874510100200100002001000030037300371110201100991001001000010000071011611299190100001003003830038300383003830038
102043003723200000611990025101251001000010010000500106745103001830037300372858832874510100200100002001000030037300371110201100991001001000010000071011611299190100001003003830038300383003830038
102043003723300000611990025101001001000010010000500106745113001830037300372858832874510100200100002001000030037300371110201100991001001000010000071011611299190100001003003830038300383003830038
1020430037232000006119900251010010010000100100005001067451030018300373003728588328745101002001000020010000300373003711102011009910010010000100000710116112991925100001003003830038300383003830038
102043003723300000611990025101001251000012510000500106745103001830037300372858832874510100200100002001000030037300371110201100991001001000010000071011611299190100001003003830038300383003830038
102043003723300000611990025101001001000010010000500106745113001830037300372858832874510100200100002001016730037300371110201100991001001000010000071211611299190100001003003830038300383003830038
102043003723300300611990025101251251000010010000500106745113001830037300372858832874410125200100002001000030037300371110201100991001001000010010071241711299190100001003003830038300383003830038
1020430037233000005321990025101001001000012510000500106745103001830037300372858832874510100200100002001000030037300371110201100991001001000010000071051611299190100001003003830038300383003830038
1020430037233000001171990025101001001000010010000626106745113001830037300372858832874510100200100002001000030037300371110201100991001001000010000071441611299190100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003723300456119900251001010100001010000501067451030018300373003728610328767100102010000201000030037300371110021109101010000100006563164329919010000103003830038300383003830038
10024300372330006119900251001010100001010000501067451030018300373003728610328767100102010058201005930085301333110021109101010000100236402242229919310000103003830038300383003830038
10024300712332206119900251001010100001110042551067612130090301323013128628628832100532010000201000030037300371110021109101010000100006555244329919110000103003830038300383003830038
100243003723300010319900251001010100001010000501067451030018300373003728610328767100102010000201000030037300371110021109101010000100006404164429919010000103003830038300383003830038
10024300372330006119900251001010100001010000501067451030018300373003728610328767100102010000201000030037300371110021109101010000100006402163329919010000103003830038300383003830038
10024300372320006119900251001010100001010000501067451030018300373003728610328767100102010000201000030037300371110021109101010000100006403164429919010000103003830038300383003830038
10024300372320006119900251001010100001010000501067451030018300373003728610328767100102010000201000030037300371110021109101010000100006404164329919010000103003830038300383003830038
10024300372330006119900251001010100001010000501067451030018300373003728610328767100102010000201000030037300371110021109101010000100006404163429919010000103003830038300383003830038
100243003723300072619900251001010100001010000501067451030018300373003728610328767100102010000201000030037300371110021109101010000100006403164229919010000103003830038300383003830038
10024300372330006119900251001010100001010000501067451030018300373003728610328767100102010000201000030037300371110021109101010000100006403164429919010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  ursqrte v0.4s, v8.4s
  ursqrte v1.4s, v8.4s
  ursqrte v2.4s, v8.4s
  ursqrte v3.4s, v8.4s
  ursqrte v4.4s, v8.4s
  ursqrte v5.4s, v8.4s
  ursqrte v6.4s, v8.4s
  ursqrte v7.4s, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802048003960010000392580100100800001008000050064000018002080039800396997106699938010020080008200800088003980039118020110099100100800001000000011151170160080036800001008004080040800408004080040
80204800396000000055292580100100800001008000050064000008002080039800396997106699938010020080008200800088003980039118020110099100100800001000000011151170160080036800001008004080040800408004080040
802048003959900000392580100100800001008000050064000008002080039800396997106699938010020080008200800088003980039118020110099100100800001000000611151170160080036800001008004080040800408004080040
802048003959900000392580100100800001008000050064000008002080039800396997106699938010020080008200800088003980039118020110099100100800001000020011151170160080036800001008004080040800408004080040
8020480039600000003925801001008000010080000500640000080020800398003969971066999380100200800082008000880039800391180202100991001008000010000004811151170160080036800001008004080040800408004080040
802048003960000000392580100100800001008000050064000008002080039800396997106699938010020080008200800088003980039118020110099100100800001000000011151170160080036800001008004080040800408004080040
802048003959900000625625801001008000010080000500640000080020800398003969971066999380100200800082008000880039800391180201100991001008000010000006311151170160080036800001008004080040800408004080040
80204800396000000039258010010080000100800005006400000800208003980039699710669993801002008000820080008800398003911802011009910010080000100000022811151170160080036800001008004080040800408004080040
802048003959900000392580100100800001008000050064000008002080039800396997136699938010020080008200800088003980039118020110099100100800001000067016811151170160080036800001008004080040800408004080040
8020480039600000003925801001008000010080000500640000080020800398003969971066999380100200800082008000880039800391180201100991001008000010000001511151170160080036800001008004080040800408004080040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)dadbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800248003960000502580010108000010800005064000001800208003980039699860370019800102080000208000080039800391180021109101080000100000502061620448003480000108004080040800408004080040
800248003959900502580010108000010800005064000000800208003980039699860370019800102080000208000080039800391180021109101080000100000502041601458003480000108004080040800408004080040
8002480039599007152580010108000010800005064000000800208003980039699860370019800102080000208000080039800391180021109101080000100000502041600348003480000108004080040800408004080040
8002480039600005252580010108000010800005064000001801348003980039699860370019800102080000208000080039800391180021109101080000100000502041600558003480000108004080040800408004080040
8002480039599002402580010108000010800005064000000800208003980039699860370019800102080000208000080039800391180021109101080000100000502071600648003480000108004080040800408004080040
800248003959900502580010108000010800005064000000800208003980039699860370019800102080000208000080039800391180021109101080000100003502031600688003480000108004080040800408004080040
8002480039599007152580010108000010800005064000000800208003980039699860370019800102080000208000080039800391180021109101080000100000502041600678003480000108004080040800408004080040
8002480039600007152580010108000010800005064000000800208003980039699860370019800102080000208000080039800391180021109101080000100000502041600548003480000108004080040800408004080040
800248003960000502580010108000010800005064000000800208003980039699860370019800102080000208000080039800391180021109101080000100010502041600368003480000108004080040800408004080040
8002480039599005252580010108000010800005064000000800208003980039699860370019800102080000208000080039800391180021109101080000100010502071600448003480000108004080040800408004080040