Firestorm: URSRA (vector, 8H) measurements

Code:

  ursra v0.8h, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	3	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	107	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	103	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	42	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	44	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	9	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  ursra v0.8h, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	39	0	145	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	105	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10205	30037	225	0	0	117	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	96	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	117	0	61	29548	25	10100	100	10000	114	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	9	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	87	0	107	29548	25	10100	100	10016	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	2	3	0	710	1	16	1	1	29634	10000	100	30134	30038	30038	30038	30132
10204	30037	225	1	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	12	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30085	30037	1	1	10201	100	99	100	100	10000	100	0	1	3	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	141	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	342	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30084	30038
10024	30037	225	42	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	270	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	330	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	306	61	29548	25	10020	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	324	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	294	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	27	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	2	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10025	30037	225	414	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  ursra v0.8h, v0.8h, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	147	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	16	0	0	29645	10000	100	30038	30038	30071	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	16	0	0	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	216	0	61	29547	25	10100	100	10000	100	10150	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	15	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	204	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	0	1	1	1	718	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	0	16	0	0	29645	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	30	0	0	726	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30132	2	1	10021	10	9	10	10	10000	10	0	0	0	0	640	0	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	24	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	0	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	15	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	0	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	30	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	0	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	269	0	294	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	0	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	15	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20336	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	0	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	24	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	640	0	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	36	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	0	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	18	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	0	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	27	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	0	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ursra v0.8h, v8.8h, #3
  movi v1.16b, 0
  ursra v1.8h, v8.8h, #3
  movi v2.16b, 0
  ursra v2.8h, v8.8h, #3
  movi v3.16b, 0
  ursra v3.8h, v8.8h, #3
  movi v4.16b, 0
  ursra v4.8h, v8.8h, #3
  movi v5.16b, 0
  ursra v5.8h, v8.8h, #3
  movi v6.16b, 0
  ursra v6.8h, v8.8h, #3
  movi v7.16b, 0
  ursra v7.8h, v8.8h, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2510

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	150	0	27	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	5	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	694	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	30	0	29	25	80116	100	80099	100	80028	500	640196	1	20045	0	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	18	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	18	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	504	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	0	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	a9	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20063	150	2	2	264	51	25	80010	10	80000	10	80000	50	640000	1	1	20029	20056	20050	3	22	80010	20	80000	20	160000	20046	20052	1	1	160021	10	9	10	10	160000	10	0	0	10044	6	2	2	18	22	3	2	1	20	23	20045	15	160000	10	20047	20047	20047	20049	20047
160024	20050	150	1	2	0	57	25	80010	10	80000	10	80000	50	640000	0	1	20031	20056	20048	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10043	6	2	2	21	26	4	2	2	17	21	20047	30	160000	10	20051	20053	20053	20051	20051
160024	20052	150	1	2	21	45	25	80010	10	80000	10	80000	50	640000	1	1	20029	20054	20153	3	22	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10046	6	2	2	19	26	4	2	2	19	20	20049	30	160000	10	20053	20053	20051	20051	20051
160024	20050	150	1	2	0	716	25	80010	10	80000	10	80000	50	640000	1	1	20027	20067	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10046	3	1	1	19	22	2	1	1	19	20	20043	16	160000	10	20049	20049	20049	20047	20049
160024	20048	150	2	2	27	45	25	80010	10	80000	10	80000	50	640000	1	1	20027	20065	20048	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10040	3	1	1	19	26	2	1	1	22	18	20043	30	160000	10	20047	20047	20047	20047	20051
160024	20050	150	1	0	0	51	25	80010	10	80000	10	80000	50	640000	0	1	20027	20054	20050	3	22	80010	20	80000	20	160000	20048	20046	1	1	160021	10	9	10	10	160000	10	0	0	10044	3	1	1	22	20	1	1	1	19	23	20043	16	160000	10	20047	20049	20049	20049	20049
160024	20052	150	0	0	9	51	25	80010	10	80000	10	80000	50	640000	0	1	20031	20065	20046	3	22	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10046	6	1	1	17	20	2	1	1	18	20	20043	15	160000	10	20047	20047	20047	20047	20047
160024	20050	150	2	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20029	20054	20046	3	22	80010	20	80000	20	160000	20048	20046	1	1	160021	10	9	10	10	160000	10	0	0	10044	3	1	1	23	22	2	1	1	18	21	20043	15	160000	10	20047	20047	20047	20049	20049
160024	20048	150	2	1	0	520	25	80010	10	80000	10	80000	50	640000	1	1	20027	20054	20050	3	22	80010	20	80000	20	160000	20052	20050	1	1	160021	10	9	10	10	160000	10	0	0	10042	6	1	1	19	22	2	1	1	18	24	20045	15	160000	10	20047	20047	20047	20047	20047
160024	20046	150	1	0	141	51	25	80010	10	80000	10	80000	50	640000	1	1	20027	20054	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	10046	6	2	2	17	24	4	2	2	18	19	20049	30	160000	10	20051	20051	20051	20051	20051

Test 5: throughput

Count: 16

Code:

  ursra v0.8h, v16.8h, #3
  ursra v1.8h, v16.8h, #3
  ursra v2.8h, v16.8h, #3
  ursra v3.8h, v16.8h, #3
  ursra v4.8h, v16.8h, #3
  ursra v5.8h, v16.8h, #3
  ursra v6.8h, v16.8h, #3
  ursra v7.8h, v16.8h, #3
  ursra v8.8h, v16.8h, #3
  ursra v9.8h, v16.8h, #3
  ursra v10.8h, v16.8h, #3
  ursra v11.8h, v16.8h, #3
  ursra v12.8h, v16.8h, #3
  ursra v13.8h, v16.8h, #3
  ursra v14.8h, v16.8h, #3
  ursra v15.8h, v16.8h, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40039	300	0	0	0	0	51	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320272	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	61	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	3	1	1	1	10118	0	16	0	0	40036	0	160000	100	40050	40049	40049	40049	40049
160204	40048	300	0	0	0	0	0	0	64	26	160116	100	160016	100	160028	500	1280196	40029	40048	40048	19976	9	19986	160128	200	160038	200	320076	40048	40048	1	1	160201	100	99	100	100	160000	100	0	2	2	2	10129	1	23	1	1	40045	0	160000	100	40049	40049	40050	40050	40049
160204	40048	300	0	0	0	0	0	0	64	26	160116	100	160016	100	160028	500	1280196	40029	40048	40048	19976	10	19986	160128	200	160038	200	320076	40049	40048	1	1	160201	100	99	100	100	160000	100	0	2	1	2	10129	1	23	1	1	40045	0	160000	100	40049	40050	40049	40050	40050
160204	40049	300	0	0	0	0	0	0	64	26	160116	100	160016	100	160028	500	1280196	40029	40048	40048	19976	10	19986	160128	200	160142	200	320076	40048	40048	1	1	160201	100	99	100	100	160000	100	0	2	2	2	10128	1	23	1	1	40046	0	160000	100	40049	40049	40049	40049	40050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	300	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	26	16	2	1	1	23	24	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	24	16	2	1	1	22	25	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	24	16	2	1	1	25	25	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	12	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	1	10022	3	1	1	20	16	2	1	1	25	27	40036	15	5	160000	10	40040	40040	40090	40040	40040
160024	40039	300	0	15	46	25	160010	10	160000	10	160000	50	1280000	1	1	40081	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	26	16	2	1	1	23	24	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	24	16	2	1	1	24	24	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	24	16	2	1	1	25	24	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	74	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	23	16	2	1	1	23	23	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	23	16	2	1	1	24	26	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	1	1	23	16	2	1	1	24	23	40036	15	5	160000	10	40040	40040	40040	40040	40040

URSRA (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations