Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

URSRA (vector, D)

Test 1: uops

Code:

  ursra d0, d1, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100020003084307311100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110003073116112630100030383038303830383038
100430372306125484410001000100039831313018303730372415328951000100020003037303711100110001373116112630100030383038303830383038
100430372206125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831313018303730372415328951000100020003037303711100110000373116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  ursra d0, d1, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500012222954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250002352954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372240007942954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830083
10204300372250001872954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372240009432954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372240002752954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000971011611296340100001003003830038300383003830038
102043003722500013122954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250001072954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cdcfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000612954825100101010000101000050427731313001803003730037282870328767100102010000202000030037300371110021109101010000100000000064002162229630010000103003830038300383003830038
100243003722500005572954825100101010000101000050427731303001803003730037282870328767100102010000202000030037300371110021109101010000100000000064002162229630010000103003830038300383003830038
100243003722500001682954825100101010000101000050427731303001803003730080282870328767100102010000202000030037300371110021109101010000100000000064002162229630010000103003830038300383003830038
100243003722500001242954825100101010000101000050427731313001803003730037282870328767100102010000202000030037300371110021109101010000100000100064002162229630010000103003830038300383008530038
10024300372250000842954825100101010000101000050427731303001803003730037282870328767100102010000202000030037300371110021109101010000100000000064002162229630010000103003830038300383003830038
10024300372250000842954825100101010000101000050427731303001803003730037282870328767100102010000202000030037300371110021109101010000100000000064002162229630010000103003830038300383003830038
10024300372250000822954825100101010000101000050427731303001803003730037282870328767100102010000202000030037300371110021109101010000100000000164002162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001803003730037282870328767100102010000202000030037300371110021109101010000100000000064002162229630010000103003830038300383003830038
10024300372250000822954825100101010000101000050427731313001803003730037282870328767100102010000202000030037300371110021109101010000100000000064002162229630010000103003830038300383003830038
10024300372250000822954825100101010000101000050427731313001803003730037282870328767100102010000202000030037300371110021109101010000100000000064002162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  ursra d0, d0, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acb5c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000000612954725101001001000010010000500427716003001830037300372827172874010100200100082002001630037300371110201100991001001000010000000000011171801600296450100001003003830038300383003830038
1020430037225000000006129547251010010010000100100005004277160030018300373003728271122875910100200100082002001630037300371110201100991001001000010000000000011171801600296460100001003003830038300383003830038
102043003722500000000612954725101001001000010010000500427716003001830037300372827172874010100200100082002001630037300371110201100991001001000010000000000011171801600296450100001003003830038300383003830038
102043003722500000000612954725101001001000010010000500427716013001830037300372827172874110100200100082002001630037300371110201100991001001000010000000000011171701600296450100001003003830038300383003830038
102043003722500000000612954725101001001000010010000500427716003001830037300372827172874010100200100082002001630037300371110201100991001001000010000000000011171701600296460100001003003830038300383003830038
102043003722500000000612954725101001001000010010000500427716013001830037300372827172874010100200100082002001630037300371110201100991001001000010000000000011171801600296450100001003003830038300383003830038
102043003722500000000612954725101001001000010010000500427716003001830037300372827172874010100200100082002001630037300371110201100991001001000010000000000011171701602296460100001003003830038300383003830038
102043003722500000000612954725101001001000010010000500427716003001830037300372827162874010100200100082002001630037300371110201100991001001000010000000000011171801600296450100001003003830038300383003830038
102043003722500000000612954725101001001000010010000500427716003001830037300372827172874010100200100082002001630037300371110201100991001001000010000001060011171801600296460100001003003830038300383003830038
102043003722500000000612954725101001001000010010000500427716013001830037300372827172874110100204100082002001630037300371110201100991001001000010000000000011171801600296460100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954725100181010000101000050427716030018300373003728291032876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716030018300373003728286032876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716030018300373003728286032876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372250612954725100101010000101014850427716030018300373003728286032876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372240612954725100101010000101000050427716030018300373003728286032876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716030018300373003728286032876710010201000020200003003730037111002110910101000010000642216222962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716030018300373003728286032876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716030018300373003728286032876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372250612954725100191010000101000050427716030018300373003728286032876710010201000020200003003730037111002110910101000010000640216422962910000103003830038300383003830038
10024300372240612954725100101010000101000050427716030018300373003728286032876710010201000020200003003730037111002110910101000010000640216342962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ursra d0, d8, #3
  movi v1.16b, 0
  ursra d1, d8, #3
  movi v2.16b, 0
  ursra d2, d8, #3
  movi v3.16b, 0
  ursra d3, d8, #3
  movi v4.16b, 0
  ursra d4, d8, #3
  movi v5.16b, 0
  ursra d5, d8, #3
  movi v6.16b, 0
  ursra d6, d8, #3
  movi v7.16b, 0
  ursra d7, d8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)0309191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420065151003605025801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010009401111011916200621600001002006620066200662006620066
1602042006515110005225801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000001111011916200621600001002006620066200662006620066
1602042006515000002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000031111011916200621600001002006620066200662006620066
160204200651500030602925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000001111011916200621600001002006620066200662006620066
1602042006515000002925801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000001111011916200621600001002006620066200662006620066
16020420065150004205025801161008001610080028500640196120045200652006561280128200800282001600562006520065111602011009910010016000010000001111011916200621600001002006620066200662006620066
1602042006515000002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000001111011916200621600001002006620066200662006620066
1602042006515000002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000001111011916200621600001002006620066200662006620066
1602042006515000002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000001111011916200621600001002006620066200662006620066
1602042006515000002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000001111011916200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l1i tlb fill (04)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200511501003892580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010010040841192842118202004315160000102004720047200472004720047
16002420050150000452580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010010039841192022118192004315160000102004720051200472004720047
16002420046150000452580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010010042841202022116172004315160000102004720047200472004720047
16002420046150000512580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010010043841182422213172004330160000102004720047200472004720047
160024200461500004525800101080000108000050640000115200272004620046322800102080000201600002004620046111600211091010160000100100391141172021117172004315160000102004720047200472004720047
16002420046150000452580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010010042841192421118212004315160000102004720047200472004720047
16002420046150001512580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010010042841172041119142004315160000102004720047200472005120051
16002420046150000512580010108000010800005064000011520027200462004632280010208000020160000200462004611160021109101016000010010043841122021114192004315160000102004720047200472004720047
16002420046150000452580010108000010800005064000011520027200502004632280010208000020160000200462004611160021109101016000010010044842192442120192004330160000102005120047200512004720047
160024200501500014525800101080000108000050640000015200312005020046322800102080000201600002004620050111600211091010160000100100401151192422119172004330160000102004720051200472005120051

Test 5: throughput

Count: 16

Code:

  ursra d0, d16, #3
  ursra d1, d16, #3
  ursra d2, d16, #3
  ursra d3, d16, #3
  ursra d4, d16, #3
  ursra d5, d16, #3
  ursra d6, d16, #3
  ursra d7, d16, #3
  ursra d8, d16, #3
  ursra d9, d16, #3
  ursra d10, d16, #3
  ursra d11, d16, #3
  ursra d12, d16, #3
  ursra d13, d16, #3
  ursra d14, d16, #3
  ursra d15, d16, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044004930000213025160108100160112102160020500128013210400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000106011110118001600400361600001004004040040400404004040040
1602044003930000030251601081001600081001600205001280132004002340039400391997711199901601202001600322003200644003940039111602011009910010016000010000100011110118001600400361600001004004040040400404004040040
160204400393000003025160108100160008100160020500128013200400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000000011110118001600400361600001004004040040400404004040040
160204400393000003025160108100160008100160020500128013200400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000000011110118001700400361600001004004040040400404004040040
16020440039300000127425160108100160008100160020500128013200400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000000011110118001600400361600001004004040040400404004040040
1602044003930004243025160108100160008100160020500128013200400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000000011110118001600400361600001004004040040400404004040040
160204400393000003025160108100160008100160020500128013200400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000000011110118001600400361600001004004040040400404004040040
160204400393000003025160108100160008100160020500128013200400204003940039199776199901601202001600322003200644003940039111602011009910010016000010002000011110118001600400361600001004004040040400404004040040
160204400393000003025160108100160008100160020500128013200400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000000011110118001600400361600001004004040040400404004040040
1602044003930000073725160108100160008100160020500128013200400204003940039199776199901601202001600322003200644003940039111602011009910010016000010000000011110118001600400361600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244003929900000462516001010160000101600005012800001154002040039400391999632001916001020160000203200004003940039111600211091010160000100000000100758415162119740036206160000104004040040400404004040040
1600244003930000000462516001010160000101600005012800001154002040039400391999632001916001020160000203200004003940039111600211091010160000100001018760100228419162117740036206160000104025140040400404004040040
1600244003930000039071125160010101600001016000050128000001540020400394003919996320019160010201600002032000040039400391116002110910101600001000000001002284291642275400362012160000104004040040400404004040040
16002440039300000121764625160010101600001016000050128000001540143400394003919996320019160010201600002032000040039400391116002110910101600001000000001002411417164118740036406160000104004040040400404004040040
1600244003930000012046251600101016000010160000501280000015400824003940039199963200191600102016000020320000400394003911160021109101016000010000000010024115291642296400364012160000104004040040400404004040145
160024400393000000046251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000429010022841101621299400364012160000104004040040400404004040040
160024400392990000046251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000000010024115291642296400364012160000104004040040400404004040040
160024400393000000052251600101016000010160000501280000015400204003940039199963200191600102016000020320000400394003911160021109101016000010000000010024115271642279400364012160000104004040040400404004040040
16002440039300000159046251603031016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000103010024115271642275400364012160000104004040040400404004040040
160024400393000004650711251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000000010024115291641275400364012160000104004040040400404004040040