Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

USHLL2 (8H)

Test 1: uops

Code:

  ushll2 v0.8h, v0.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)031e3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
100420371508216862510001000100026452112018203720371571318951000100010002037203711100110000073216111786100020382038203820382038
100420371508216862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371608416862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371606116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716010116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371606116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371606116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371606116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371606116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371606116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  ushll2 v0.8h, v0.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire (01)cycle (02)03080b18191e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204200371550000396061196862510100100100001001000050028475211200180200372003718421318816101002001000020010000200372003711102011009910010010000100000000071021622197910100001002003820038200382003820038
102042003715500000061196862510100100100001001000050028475210200180200372003718421318745101002001000020010000200372003711102011009910010010000100000000071021622197910100001002003820038200382003820038
10204200371550000354061196862510100100100001001000050028475211200180200372003718421318745101002001000020010000200372003711102011009910010010000100000000071021622197910100001002003820038200382003820038
10204200371550000312061196862510100100100001001000050028475211200180200372003718421318745101002001000020010000200372003711102011009910010010000100000000071021622197910100001002003820038200382003820038
1020420037155000093061196862510100100100001001000050028475211200180200372003718421318745101002001000020010000200372003711102011009910010010000100000000071021622197910100001002003820038200382003820038
10204200371550000333061196862510100100100001001000050028475210200180200372003718421318745104322001000020010000200372003711102011009910010010000100000000071022522197910100001002003820038200382003820038
10204200371550000288061196862510100100100001001000050028475211200180200372003718421318745101002001000020010000200372003711102011009910010010000100000000071021622197910100001002003820085200382008620038
102042008615610111561045801965210210178127100481401076067828525381201980202282027618434251883710887220108312161082820229202275110201100991001001000010000210100352732216321995229100001002027420265202772027820276
1020420276157114267244026131962014510203142100721391091271428475210202340202772032418443401888511288222111652301116520412203726110201100991001001000010000002140602888273322009732100001002013320409203732037020419
10204203711581078105961636211959818610244128100841441106472028563690202700204212037118446381889210433224111692301066620466204259110201100991001001000010022402155900887399232004033100001002040820420204192036020407

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire (01)cycle (02)031e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a8branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
100242003715006119686251001010100001010000502847521120018020037200371844331876710010201000020100002003720037111002110910101000010000640416551983810000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018020037200371844331876710010201000020100002003720037111002110910101000010000640516441978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521120018020037200371844331876710010201000020100002003720037111002110910101000010000640516551978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018020037200371844331876710010201000020100002003720037111002110910101000010000640616551978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521120018020037200371844331876710010201000020100002003720037111002110910101000010000661416441978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521120018020037200371844331876710010201000020100002003720037111002110910101000010000640516551978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521120018020037200371844331876710010201000020100002003720037111002110910101000010000640516441978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521120018020037200371844331876710010201000020100002003720037111002110910101000010000640516441978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521120018020037200371844331876710010201000020100002003720037111002110910101000010000640516551978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521120018020037200371844331876710010201000020100002003720037111002110910101000010000640616561978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  ushll2 v0.8h, v8.16b, #3
  ushll2 v1.8h, v8.16b, #3
  ushll2 v2.8h, v8.16b, #3
  ushll2 v3.8h, v8.16b, #3
  ushll2 v4.8h, v8.16b, #3
  ushll2 v5.8h, v8.16b, #3
  ushll2 v6.8h, v8.16b, #3
  ushll2 v7.8h, v8.16b, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)0307080a0b18191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc2c5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
8020420057156000000120005025801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118021600200350800001002003920039200392003920039
802042003815500000015002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118001600200350800001002003920039200392003920039
80204200381550000000002925801081008000810080020500640132120019201372003899776998980120200800322008003220038200381180201100991001008000010000000001115118001600200350800001002003920039200392003920039
80204200381550000000002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118001600200350800001002003920039200392003920039
80204200381550000000002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118001600200350800001002003920039200392003920039
8020420038155000000000368925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118001600200350800001002003920039200392003920039
80204200381560000000002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000301115118001600200350800001002003920039200392003920039
802042003815600000000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000011151180016002003521800001002003920039200392003920039
80204200381550000000007125801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118001600200350800001002003920039200392003920039
802042003815000000000020825801081008000810080020500640132120023200382003899776998980120200800322008003220038200381180201100991001008000010000000001115118001600200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)030f18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a8a9accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
800242031316404880461631741248057510808411080677506468920020171200382003899893100118001020800002080000200382003811800211091010800001000005020116112003580000102003920039200392003920039
800242003816100000672580010108000010800005064000000200192003820038998912100118001020800002080000200382003811800211091010800001000035020116112003580000102003920039200392003920039
80024200381550000039258001010800001080000506400000020019200382003899893100118001020800002080000200382003811800211091010800001000005020116112003580000102003920039200392003920039
8002420038156000453039258010410800001080000506400000020019200982003899893100118001020800002080000200382003811800211091010800001000005020116112011480000102003920039200392003920089
80024200381550000039258001010800001080000506400000020019200382003899893100118001020800002080000200382003811800211091010800001000005020116112003580000102003920039200392003920039
80024200381560000039258001010800001080000506400000020019200382003899893100118001020800002080000200382003811800211091010800001000005020116112003580000102003920039200392003920039
800242003816100000123258001010800001080000506400000120019200382003899893100118001020800002080000200382003811800211091010800001000005020116112003580000102003920039200392003920039
80024200381550000039258001010800001080000506400000020019200382003899893100118001020800002080000200382003811800211091010800001000005020116112003580000102003920039200392009320039
8002420038156010901366258001010800001080096506400000120019200382008899893100118001020800002080099200382003811800211091010800001000005020116112003580000102003920039200392003920039
8002420038155000273039258001010800001080000506400000020019200382003899893100118001020800002080000200382003811800211091010800001000005020116112003580000102003920039200392003920039