Firestorm: USHLL2 (8H) measurements

Code:

  ushll2 v0.8h, v0.16b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	82	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	2	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	82	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	84	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	101	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->2

Code:

  ushll2 v0.8h, v0.16b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	155	0	0	0	0	396	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	0	20037	20037	18421	3	18816	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	0	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	354	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	0	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	312	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	0	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	93	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	0	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	333	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	0	20037	20037	18421	3	18745	10432	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	25	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	288	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	0	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20085	20038	20086	20038
10204	20086	156	1	0	1	1	156	104	580	19652	102	10178	127	10048	140	10760	678	2852538	1	20198	0	20228	20276	18434	25	18837	10887	220	10831	216	10828	20229	20227	5	1	10201	100	99	100	100	10000	100	0	0	2	1	0	10035	2	732	2	16	3	2	19952	29	10000	100	20274	20265	20277	20278	20276
10204	20276	157	1	1	4	2	672	440	2613	19620	145	10203	142	10072	139	10912	714	2847521	0	20234	0	20277	20324	18443	40	18885	11288	222	11165	230	11165	20412	20372	6	1	10201	100	99	100	100	10000	100	0	0	0	0	2	14060	2	888	2	73	3	2	20097	32	10000	100	20133	20409	20373	20370	20419
10204	20371	158	1	0	7	8	1059	616	3621	19598	186	10244	128	10084	144	11064	720	2856369	0	20270	0	20421	20371	18446	38	18892	10433	224	11169	230	10666	20466	20425	9	1	10201	100	99	100	100	10000	100	2	2	4	0	2	15590	0	887	3	99	2	3	20040	33	10000	100	20408	20420	20419	20360	20407

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	4	16	5	5	19838	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	5	16	4	4	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	5	16	5	5	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	6	16	5	5	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	661	4	16	4	4	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	5	16	5	5	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	5	16	4	4	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	5	16	4	4	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	5	16	5	5	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	6	16	5	6	19786	10000	10	20038	20038	20038	20038	20038

Test 3: throughput

Count: 8

Code:

  ushll2 v0.8h, v8.16b, #3
  ushll2 v1.8h, v8.16b, #3
  ushll2 v2.8h, v8.16b, #3
  ushll2 v3.8h, v8.16b, #3
  ushll2 v4.8h, v8.16b, #3
  ushll2 v5.8h, v8.16b, #3
  ushll2 v6.8h, v8.16b, #3
  ushll2 v7.8h, v8.16b, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20057	156	0	0	0	0	0	0	120	0	0	50	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	2	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	15	0	0	29	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	0	0	0	29	25	80108	100	80008	100	80020	500	640132	1	20019	20137	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	0	0	0	29	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	0	0	0	29	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	0	0	0	3689	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	156	0	0	0	0	0	0	0	0	0	29	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	3	0	1	1	1	5118	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	156	0	0	0	0	0	0	0	0	0	29	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20035	21	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	0	0	0	71	25	80108	100	80008	100	80020	500	640132	1	20019	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	150	0	0	0	0	0	0	0	0	0	208	25	80108	100	80008	100	80020	500	640132	1	20023	20038	20038	9977	6	9989	80120	200	80032	200	80032	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	1	1	1	5118	0	0	16	0	0	20035	0	80000	100	20039	20039	20039	20039	20039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0f	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20313	164	0	4	8	804	616	3174	124	80575	10	80841	10	80677	50	646892	0	0	20171	20038	20038	9989	3	10011	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	1	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	67	25	80010	10	80000	10	80000	50	640000	0	0	20019	20038	20038	9989	12	10011	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	3	5020	1	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	0	0	20019	20038	20038	9989	3	10011	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	1	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	156	0	0	0	453	0	39	25	80104	10	80000	10	80000	50	640000	0	0	20019	20098	20038	9989	3	10011	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	1	16	1	1	20114	80000	10	20039	20039	20039	20039	20089
80024	20038	155	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	0	0	20019	20038	20038	9989	3	10011	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	1	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	156	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	0	0	20019	20038	20038	9989	3	10011	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	1	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	161	0	0	0	0	0	123	25	80010	10	80000	10	80000	50	640000	0	1	20019	20038	20038	9989	3	10011	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	1	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	0	0	20019	20038	20038	9989	3	10011	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	1	16	1	1	20035	80000	10	20039	20039	20039	20093	20039
80024	20038	156	0	1	0	9	0	1366	25	80010	10	80000	10	80096	50	640000	0	1	20019	20038	20088	9989	3	10011	80010	20	80000	20	80099	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	1	16	1	1	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	0	0	273	0	39	25	80010	10	80000	10	80000	50	640000	0	0	20019	20038	20038	9989	3	10011	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	1	16	1	1	20035	80000	10	20039	20039	20039	20039	20039

USHLL2 (8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations