Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USHL (vector, 2D)

Test 1: uops

Code:

  ushl v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716066116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715036116872510001000100026468002018203720371572318951000100020002037203711100110001073116111787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160726116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716008216872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716096116872510001000100026468012018203720371572318951000100020002037203711100110000373116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  ushl v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715506119643251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037155031819687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715506119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715606119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037156061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001002607101161119791100001002003820038200382003820038
102042003715606119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100037101161119791100001002003820038200382003820038
102042003715506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037155025119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037155126119687251010010010000100100005002847680020018200852003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500012006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010100640216221978510000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010030640216221978510000102003820038200382008620038
1002420037150130006119676621002310100001010000552847680020018020037200371844431876710010201000020200002003720037111002110910101000010030640216221978510000102003820038200382003820038
10024200371500000072619687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010060640216221978510000102003820038200382003820038
100242003715000000286619687251001010100481010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010130640216221978510000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010230640216221978510000102003820038200382003820038
10024200371500100010319687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  ushl v0.2d, v1.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155000000061196872510100100100001001000050028476800020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000000710011611197910100001002003820038200382003820038
1020420037156000000061196872510100100100001001000050028476801520018200372003718422318745101002001000020020000200372003711102011009910010010000100000000000710011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800020018200372003718422318745101002001000020020000200372003711102011009910010010000100000020300710011611197910100001002003820038200382003820038
1020420037156000000061196872510100100100001001000050028476800020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000000710011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000000710011611197910100001002003820038200382003820038
10204200371550000000726196872510100100100001001000050028476800020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000001710011611197910100001002003820232200382003820038
10204200371550000210061196873610100100100001001000050028476800020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000000710011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000000710011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000000735011611197910100001002003820038200382003820038
102042003715500000006119687251010010010000100100005002847680002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000013800710011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715600611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211090101010000100006402162219785010000102003820038200382003820038
100242003715500611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211090101010000100006402162219785010000102003820038200382003820038
100242003715500611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003721100211090101010000100006402162219785010000102003820038200382003820038
100242003715500611968725100101010000101000050284768002001832003720037184443187671001020100002020000200372003711100211090101010000100016402162219785010000102003820038200382003820038
1002420037155030611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211090101010000100006402162219785010000102003820038200382003820038
1002420037156095261968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211090101010000100006402162219785010000102003820038200382003820038
1002420037155006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110901010100001001506402162219785010000102003820038200382003820038
100242003715600611968725100101010000101000050284768002001802003720037184443187671001020100002020000200862003711100211090101010000100006402162219785010000102003820038200382003820038
100242003715500611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211090101010000100006402162219785010000102003820038200382003820038
100242003715500611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211090101010000100006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  ushl v0.2d, v8.2d, v9.2d
  ushl v1.2d, v8.2d, v9.2d
  ushl v2.2d, v8.2d, v9.2d
  ushl v3.2d, v8.2d, v9.2d
  ushl v4.2d, v8.2d, v9.2d
  ushl v5.2d, v8.2d, v9.2d
  ushl v6.2d, v8.2d, v9.2d
  ushl v7.2d, v8.2d, v9.2d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420038156004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001002300511031611200350800001002003920039200392003920039
8020420038156008225801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
8020420038156004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
80204200381551206825801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000100511011611200350800001002003920039200392003920039
8020420038155004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
8020420038155004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
80204200381560042025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000100511011611200350800001002003920039200392003920039
80204200381561204025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
8020420038155004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
8020420038155004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd2d5map dispatch bubble (d6)d9dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048156153925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050200916008182003580000102003920039200392003920039
80024200381550172925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050200916007172003580000102003920039200392003920039
80024200381550392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020017160017172003580000102003920039200392003920039
8002420038155039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000502001716008172003580000102003920039200392003920039
80024200381550392580010108000010800005064000002001920038200389996310018800102080000201602642003820038118002110910108000010005020014160017172003580000102003920039200392003920039
80024200381550602580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020014160018172003580000102003920039200392003920039
800242003815503925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050200816001782003580000102003920039200392003920039
80024200381551239258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000502001716008172003580000102003920039200392003920039
80024200381550392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020017160018172008580000102003920039200392003920039
8002420038155039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000502001716001762003580000102003920039200392003920039