Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USHL (vector, 4S)

Test 1: uops

Code:

  ushl v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203718019016872510001000100026468012018203720371572318951000100020002037203711100110001373116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716126116872510001000100026468002018203720371572318951000100020002037203711100110000073116112034100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  ushl v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715510000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715600000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715600000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715500010006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715500000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715500000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037155000090017219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071014211197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037155000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371550000006119687251001010100001010000502847680120018200372003718444251875510010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037160000000891968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371550000120611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010020000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  ushl v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715500276119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100200007101421119791100001002003820038200382003820038
10204200371551006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715500246119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371560006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371551006119687251010010010000100100005002847680120019200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371560006119687251010010010000100100005002847680120022200372003718422318745101002001000020020000200372003711102011009910010010000100000007101160119791100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680120018200372003718422718741101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100006404243319785010000102003820038200382003820038
100242003715500061196872510010101000010100005028489630200180200372003718444318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038
1002420037155000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000516403163319785010000102003820038200382003820038
100242003715500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038
100242003715600089196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038
100242003715500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038
100242003715500084196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038
100242003715600061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038
100242003715500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038
100242003715500061196872510010101000010100005028476800200180200372003718444318767101602010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  ushl v0.4s, v8.4s, v9.4s
  ushl v1.4s, v8.4s, v9.4s
  ushl v2.4s, v8.4s, v9.4s
  ushl v3.4s, v8.4s, v9.4s
  ushl v4.4s, v8.4s, v9.4s
  ushl v5.4s, v8.4s, v9.4s
  ushl v6.4s, v8.4s, v9.4s
  ushl v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005915500402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051102161120035800001002003920039200392003920039
802042003815500822580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815600402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
8020420038155120402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100100051101161120035800001002003920039200392003920039
8020420038155150682580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815500402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815600402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815500402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815500402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815500402580100100800001008000050064000012001920038200859973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020216112003580000102003920039200392003920039
8002420038155000679258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020116222003580000102003920039200392003920039
800242003815500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020216112003580000102003920039200392003920039
800242003815500060258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000305020216222003580000102003920039200392003920039
800242003815500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020216112003580000102003920039200392003920039
800242003815500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020116112003580000102003920039200392003920039
800242003815500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000305020116222003580000102003920039200392003920039
800242003815600039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020216212003580000102003920039200392003920039
800242003815600039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020216112003580000102003920039200392003920039
800242003815500039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000005020116112003580000102003920039200392003920039