Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USHL (vector, D)

Test 1: uops

Code:

  ushl d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715008216872510001000100026468002018203720371572318951000100020002037203711100110001073216221787100020382038203820382038
10042037150014816872510001000100026468012018203720371572318951000100020002037203711100110001073216221787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203716006116872510001000100026468012018203720371572318951000100020002037203711100110001073116111787100020382038203820382038
1004203716006116872510001000100026468012018203720371572318951000100020002037203711100110001073216221787100020382038203820382038
10042037150010316872510001000100026468002018203720371572318951000100020002037203711100110001073216221787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110001073216221787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110001073216221787100020382038203820382038
1004203716006116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  ushl d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011601119791100001002003820038200382003820038
10204200371550002321968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011601119791100001002003820038200382003820038
1020420037155000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011601119791100001002003820038200382003820038
1020420037155000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011601119791100001002003820038200382003820038
1020420037156000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010003071011601119791100001002003820038200382003820038
1020420037156000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010010071011601119791100001002003820038200382003820038
10204200371550007261968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011601119791100001002003820038200382003820038
1020420037155000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011601119791100001002003820038200382003820038
1020420037155000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010010071011601119791100001002003820038200382003820038
1020420037155000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011601119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000025119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
10024200371500000023219687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006402163319785010000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680020018200372003718444318767100102010168202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680120018200372003718444718767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000008219687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  ushl d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155000100611968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001000000071021622197910100001002003820038200382003820038
1020420037156000000611968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001000000071021622197910100001002003820038200382003820038
1020420037155000000611968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001000000071021622197910100001002003820038200382003820038
1020420037155000000611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000000071021622197910100001002003820038200382003820038
10204200371560000001731968725101001001000010010000500284768002001862003720037184229187451010020010000200200002003720037111020110099100100100001000000071021622197910100001002003820038200382003820038
1020420037155000000611968745101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000000071021622197910100001002003820038200382003820038
1020420037155000000611968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001000300071021622197910100001002003820038200382003820038
1020420037155000000611968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001000011171711611198060100001002003820038200382003820038
1020420037156110000611968725101001001000010010000500284768002001802003720037184296187401010020010008200200162003720037111020110099100100100001000011171711611198060100001002003820038200382003820038
1020420037155110000611968725101001001000010010000500284768002001802003720037184296187401010020010008200200162003720037111020110099100100100001000011171811611198060100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200741551100015264611968725100101010000101060850284768002001820037200371844431876710316201000020200002003720037111002110910101000010030906402162219785010000102003820038200382003820038
100242003715510000300841968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006422162219785010000102003820038200382003820038
10024200371550000000921968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371550000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402163219787010000102003820038200382003820038
100242003715500000001671968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402166219785010000102003820038200382003820038
10024200371550000090611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371560000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371550000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371550000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
100242003715500000120611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219787010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  ushl d0, d8, d9
  ushl d1, d8, d9
  ushl d2, d8, d9
  ushl d3, d8, d9
  ushl d4, d8, d9
  ushl d5, d8, d9
  ushl d6, d8, d9
  ushl d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058155000004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000051103161120035800001002003920039200392003920039
80204200381550000024125801001008000010080000620640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003816100000974258010010080000100800005006400001200192003820038997303999680100200800002001600002003820038118020110099100100800001000018051101161120035800001002003920039200392003920039
8020420038155000004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
80204200381550000040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000039051101161120035800001002003920039200392003920039
8020420038155000004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
8020420038155000004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392009020039
80204200381550126884025803061008000011480000500640000120019200382003899900399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
80204200381560000013525801001008000010080000500640000120019200382003899730399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
8020420038155000004025801001008000010080000500640000020019200382003899730399968010020080000200160000200382003811802011009910010080000100100051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fabaccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039155010000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020271624252003580000102003920039200392003920039
8002420038155020000392580010108000010800005064000002001920038200389996310045800102080000201600002003820038118002110910108000010005020221625252003580000102003920039200392003920039
8002420038155010000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020201625202003580000102003920039200392003920039
80024200381550100001792580010108010410800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020201626212003580000102003920039200392003920039
80024200381550200012392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020261627272003580000102003920039200392003920039
8002420038155010000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010035020261627272003580000102003920039200392003920039
80024200381550001012392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020271627272003580000102003920039200392003920039
8002420038155000000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010035020251626292003580000102003920039200392003920039
8002420038155000009392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020211625182003580000102003920039200392003920039
8002420038155000000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020271625272003580000102003920039200392003920039