Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USHR (vector, 2D)

Test 1: uops

Code:

  ushr v0.2d, v0.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000373116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715126116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371606116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371606116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371606116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371606116862510001000100026452102018203720371571318951000100010002037203711100110001073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  ushr v0.2d, v0.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037156006119686251010010010000100100005002847521120020200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037156038219686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371550816119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037155006119686251010010010000100100005502847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037155006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371550010319686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037155006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037155006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037155006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037155006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0309181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150001201051968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010210640216221978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000120611967525100101010000101000055284878512001820037200371844331876710010201000022100002003720037111002110910101000010200640216221978610000102003820038200382003820038
1002420037150100104611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
1002420037150024501031968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640216221978610000102003820038200382003820038
10024200371500090611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010020640216221978610000102003820038200382013320038

Test 3: throughput

Count: 8

Code:

  ushr v0.2d, v8.2d, #3
  ushr v1.2d, v8.2d, #3
  ushr v2.2d, v8.2d, #3
  ushr v3.2d, v8.2d, #3
  ushr v4.2d, v8.2d, #3
  ushr v5.2d, v8.2d, #3
  ushr v6.2d, v8.2d, #3
  ushr v7.2d, v8.2d, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006115612029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100001115118160020035800001002003920039200392003920039
80204200381560029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100001115118160020035800001002003920039200392003920039
80204200381550071258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100001115118160020035800001002003920039200392003920039
802042003815560292580108100800081008002050064013202001920110200989977699898012020080134200800322003820038218020110099100100800001005431115118160020035800001002003920039200392003920039
80204200381550029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100001115118160020035800001002003920039200392003920039
80204200381550029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100001115118160020035800001002003920039200392003920039
80204200381550029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100031115118160020035800001002003920039200392003920039
8020420038155002925801081008000810080020500640132120019200382003899776998980120200800322008003220038200381180201100991001008000010001471115118160020035800001002003920039200392003920039
80204200381550029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100031115118160020035800001002003920039200392003920039
802042003815500292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000601115118160020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005115500000081258001010800001080000506400001120019200382003899963100188001020800002080000200382003811800211091010800001000050205160332003580000102003920039200392003920039
800242003815500000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000050202160332003580000102003920039200392003920039
800242003815510000039258010310800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000050203160232003580000102003920039200392003920039
800242003815500000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000050203160322003580000102003920039200392003920039
800242003815600000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000050202160332003580000102003920039200392003920039
800242003816100000039258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000050203160332003580000102003920039200392003920039
800242003815500000039258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000050203160332003580000102003920039200392003920039
800242003815500000039258001010800001080000506400000020019200382003899963100188001020800002080000200382003811800211091010800001000050202160332003580000102003920039200392003920039
800242003815500000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000050203160332003580000102003920039200392003920039
800242003815500000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000050202160322003580000102003920039200392003920039