Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USHR (vector, 4S)

Test 1: uops

Code:

  ushr v0.4s, v0.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716009716862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037151206116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037160010316862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150012416862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037163012616862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150058116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037160023516862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  ushr v0.4s, v0.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715500103196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371550061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371610061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371550061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371550061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371550061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371550061196862510100100100001001000050028475210200182003720084184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371560061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371550061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371550061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003716106119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
100242003715506119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
100242003715506119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
100242003715506119686251001010100001010000502847521020018200372003718457318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
100242003715506119686251001010100001010000502847521120018200372003718443318767100102010000201016820037200371110021109101010000100640216221978610000102003820038200382003820038
100242003715506119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037155031719686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640416221978610000102003820038200382003820038
100242003715506119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100669216221978610000102003820038200382003820038
100242003715506119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
10024200371550611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010585640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  ushr v0.4s, v8.4s, #3
  ushr v1.4s, v8.4s, #3
  ushr v2.4s, v8.4s, #3
  ushr v3.4s, v8.4s, #3
  ushr v4.4s, v8.4s, #3
  ushr v5.4s, v8.4s, #3
  ushr v6.4s, v8.4s, #3
  ushr v7.4s, v8.4s, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059160000219258010810080008100800205006401321200192003820038997769986801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
802042003815500029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100003111511801620035800001002003920039200392003920039
802042003815500071258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
802042003815500029438020410080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
802042003815500029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100043111511801620035800001002003920039200392003920039
802042003815500029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
802042003815500029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
802042003815500029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100003111513601620035800001002003920039200392003920039
802042003815500029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000111511801620035800001002003920039200392003920039
802042003815500029258010810080008100800205006401320200192003820038997769989801202008003220080032200382003811802011009910010080000100000111511811620035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391550000039258001010800001080000506400000020019200382003899963100188001020800002080099200382003811800211091010800001000300050200013161292003580000102003920039200392003920039
8002420038156000390392580010108000010800005064000000200192003820038999631001880010208000020802932010120038118002110910108000010000000502000141614162003580000102003920039200392003920039
800242003815500000392580010108000010800005064000000200192003820038999631001880010208000020800002003820038118002110910108000010000000502000101615122003580000102003920039200392003920039
800242024615500090392580010108000010800005064000010200192003820038999631001880010208000020800002003820038118002110910108000010000000502000151618142003580000102003920039200392003920039
800242003815500000392580010108000010800005064000000200192003820038999631001880010208000020800002003820038118002110910108000010000000502000151610142003580000102003920039200392003920039
8002420038155010003925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100000180502054141613102003580000102003920039200392003920039
800242003816100000392580010108000010800005064000010200192003820038999631001880010208000020800002003820038118002110910108000010000000502000151614142003580000102003920039200392003920039
800242003815500000392580010108000010800005064000005200192003820038999631001880010208000020800002003820038118002110910108000010000000502054121616132003580000102003920089200392003920039
80024200381550000352392580010108000010800005064000010200192003820038999631001880010208000020800002003820038118002110910108000010000000502054151615132003580000102003920039200392003920039
800242003815500000392580010108000010800005064000000200192003820038999631001880010208000020800002003820038118002110910108000010000000502000111613162003580000102003920039200392003920039