Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USHR (vector, 8H)

Test 1: uops

Code:

  ushr v0.8h, v0.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073216111786100020382038203820382038
10042037160611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037160611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371501031686251000100010002645212018203720371571318951000100010002037203711100110001073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037169611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037160611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100010002037203711100110009073124111786100020382038203820382038
10042037160611686251000100010002645212018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  ushr v0.8h, v0.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbbc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155000000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000000000710116111979100100001002003820038200382003820137
1020420037155000000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000300000710116111979100100001002003820038200382003820038
1020420037155000000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000000000710116111979100100001002003820038200382003820038
1020420037155000000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000000000710116111979100100001002003820038200382003820038
1020420037155000000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000000000710116111979100100001002003820038200382003820038
1020420037155000000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000000000710116111979100100001002003820038200382003820038
1020420037155000000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000000000710116111979100100001002003820038200382003820038
1020420037155000000061196862510100100100001001000050028475211200182003720037184213187641010020010000200100002003720037111020110099100100100001000000000000710116111979100100001002003820038200382003820038
10204200371550000120061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000001000000710116111979100100001002003820038200382003820038
102042003715600001200110196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000000000710116111979100100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acl1d cache miss ld nonspec (bf)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000060611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
10024200371500000270821968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000003006402162219786010000102003820038200382003820038
1002420037150000060611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162419786010000102003820038200382003820038
1002420037149000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
10024200371500000270611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000001110611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  ushr v0.8h, v8.8h, #3
  ushr v1.8h, v8.8h, #3
  ushr v2.8h, v8.8h, #3
  ushr v3.8h, v8.8h, #3
  ushr v4.8h, v8.8h, #3
  ushr v5.8h, v8.8h, #3
  ushr v6.8h, v8.8h, #3
  ushr v7.8h, v8.8h, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420057155007125801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100270611151180160020035800001002003920039200392003920039
8020420038155005042580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010040011151180160020035800001002003920039200392003920039
802042003815600292580108100800081008025050064019620028200482004899769998680128200800382008003820048200481180201100991001008000010030022251281231120045800001002004920049200502004920049
802042004915500642780116100800161008002850064019620028200482004899769998680128200800382008003820049200481180201100991001008000010000022251281231120045800001002005020049200492004920049
8020420048156006426801161008001610080028500640196200282004820048997610998680128200800382008003820049200491180201100991001008000010000022251281231120045800001002004920049200502004920049
8020420049155006426801161008001610080028500640196200282004820048997610998680128200800382008003820049200491180201100991001008000010000022251281231120046800001002004920049200492004920049
8020420048155006426801161008001610080028500640196200282004820048997610998680128200800382008003820049200481180201100991001008000010000022251291231120045800001002005020050200502004920049
8020420048155006926801161008001610080028500640196201512004820048997610998680128200800382008003820048200481180201100991001008000010000022251281231120045800001002004920049200492004920049
80204200481560064268011610080016100800285006401962002820048200489976999868012820080038200800382004920048118020110099100100800001003201222251291231120045800001002004920049200492005020050
8020420048155006427801161008001610080028500640196200282004820049997699986801282008003820080038200482004811802011009910010080000100700622251281231120045800001002005020050200492004920050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200501550123925800101080000108000050640000010200192003820038999631001880010208000020800002003820038118002110910108000010000005020006166620035080000102003920039200392003920039
80024200381550123925800101080000108000050640000000200192003820038999631001880010208000020800002003820038118002110910108000010001005020007166620035080000102003920039200392003920039
800242003815600392580010108000010800005064000001020019200382003899963100188001020800002080000200382003811800211091010800001000104905020006169720075080000102003920102200392003920039
80024200381561039258001010800001080000506400000102001920038200389996310018800102080000208000020038200381180021109101080000100000215020006166720035080000102003920039200392003920039
8002420038155006025800101080000108000050640000010200192003820038999631001880010208000020800002003820038118002110910108000010000005020007166620035080000102003920039200392003920039
8002420038156003925800101080000108000050640000010200192003820038999631001880010208000020800002003820038118002110910108000010000005020006167720035080000102003920039200392003920039
80024200381550032425800101080000108000050640000010200192003820038999631001880010208000020800002003820038118002110910108000010001005020006166720035080000102003920039200392003920039
8002420038155033925800101080000108000050640000110200192003820038999631001880010208000020800002003820038118002110910108000010000005020006166720035080000102003920039200392003920039
80024200381550039258001010800001080000506400000102001920038200389996310018800102080000208000020038200381180021109101080000100000845020006167620035080000102003920039200392003920039
8002420038155003925800101080000108000050640000000200192003820038999631001880010208000020800002003820038118002110910108000010000005020007167720035080000102003920039200392003920039