Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USHR (vector, D)

Test 1: uops

Code:

  ushr d0, d0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715000611686251000100010002645210020182037203715713189510001000100020372037111001100000730116111786100020382038203820382038
1004203716000611686251000100010002645210520182037203715713189510001000100020372037111001100000730116111786100020382038203820382038
1004203716000611686251000100010002645210020182037203715713189510001000100020372037111001100010730116111786100020382038203820382038
1004203715000611686251000100010002645210020182037203715713189510001000100020372037111001100000730116111786100020382038203820382038
10042037160012611686251000100010002645211020182037203715713189510001000100020372037111001100000730116111837100020382038203820382038
1004203715000611686251000100010002645210020182037203715713189510001000100020372037111001100003730116111786100020382038203820382038
1004203715000611686251000100010002645210020182037203715713189510001000100020372037111001100000735116111786100020382038203820382038
1004203716000611686251000100010002645210020182037203715713189510001000100020372037111001100000730116111786100020382038203820382038
1004203715000611686251000100010002645210020182037203715713189510001000100020372037111001100003730116111786100020382038203820382038
1004203716000611686251000100010002645210020182037203715713189510001000100020372037111001100000730116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  ushr d0, d0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715506119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715506119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715506119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715506119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037155010319686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715606119686251010010010000100100005002847521020018200372003718355318745101002001000020010000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715506119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715506119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715506119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715506119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037155206119686251001010100001010000502847521120018200372003718443031876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
10024200371552053619686251001010100001010000502847521020018200372003718443031876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
1002420037155006119686251001010100001010000502847521020018200372003718443031876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
1002420037155206119686251001010100001010000502847521020018200372003718443031876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
10024200371552010319686251001010100001010000502847521020018200372003718443031876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
10024200371622098519686251001010100001010000502847521120018200372003718443031876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
1002420037155006119686251001010100001010000502847521120018200372003718443031876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
1002420037155006119686251001010100001010000502847521120018200372003718443031876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
1002420037155006119686251001010100001010000502847521120018200372003718443031876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
1002420037155006119686251001010100001010000502847521120018200372003718443031876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  ushr d0, d8, #3
  ushr d1, d8, #3
  ushr d2, d8, #3
  ushr d3, d8, #3
  ushr d4, d8, #3
  ushr d5, d8, #3
  ushr d6, d8, #3
  ushr d7, d8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060156003342580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151182163320035800001002003920039200392003920039
80204200381550010322580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151183163420035800001002003920039200392003920039
8020420038155005092580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151183163320035800001002003920039200392003920039
802042003815500292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001002011151183162320035800001002003920039200392003920039
8020420038156001932580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151184164320035800001002003920039200392003920039
8020420038155001682580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151184162220035800001002003920039200392003920039
8020420038155002352580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151184164320035800001002003920039200392003920039
8020420038155001802580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151183163420035800001002003920039200392003920039
8020420038155001572580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151183163420035800001002003920039200392003920039
8020420038155001642580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151184163420035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch ret (8f)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd2d5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511560392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021100910108000010105020018165520035080000102003920039200392003920039
8002420038155039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110091010800001000502004166420035080000102008820091200392003920039
80024200381561839258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110091010800001020502006165620035080000102003920039200392003920039
8002420038155039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110091010800001013502006166620035080000102003920039200392003920039
80024200381600129258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110091010800001000502004164520035080000102003920039200392003920039
8002420038155039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110091010800001000502006166920035080000102003920039200392003920039
8002420038156039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110091010800001000502006169420035080000102003920039200392003920039
8002420038155039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110091010800001000502008165320035080000102003920039200392003920039
80024200381550392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021100910108000010235020081610920035080000102003920039200392003920039
80024200381550392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021100910108000010005020041610420035080000102003920039200392003920039