Firestorm: USQADD (scalar, B) measurements

Code:

  usqadd b0, b1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1161	2320	3037	3037	1	1	1001	1000	2	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	3	88	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	12	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	126	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  usqadd b0, b1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	233	0	0	0	0	88	0	168	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	202	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	2	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	1	1	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	4	2	0	0	0	710	1	16	1	1	29706	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	1	0	2	0	0	0	61	29548	25	10140	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28752	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	2	756	2	16	1	1	29811	26	10000	100	30279	30464	30273	30468	30372
10204	30467	235	0	5	9	1194	440	0	6065	29476	124	10219	130	10064	128	11043	754	4288169	0	30306	30457	30263	28279	44	28836	11027	230	11319	216	21528	30464	30275	10	1	10201	100	99	100	100	10000	100	0	0	1	0	0	710	1	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30181
10204	30131	233	0	0	1	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30054	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	151	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	32	1	2	29704	22	10000	100	30038	30086	30085	30038	30038
10204	30037	233	0	0	0	0	0	0	89	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	82	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29686	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	233	0	0	0	0	0	324	29548	63	10020	12	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	0	0	0	0	640	4	16	4	4	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	9	0	640	4	16	4	4	29630	2	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	0	0	0	766	29548	25	10010	10	10032	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	3	0	640	4	16	4	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	1	0	0	0	0	173	29548	45	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	3	0	640	4	16	4	3	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	0	0	0	439	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	3	4	29630	0	10000	10	30038	30038	30038	30179	30038
10024	30037	233	0	0	0	0	0	124	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	3	4	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	241	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	5	2	0	0	640	3	16	3	4	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	89	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	4	4	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	97	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30133	28287	3	28767	10160	20	10325	22	20336	30037	30037	2	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	0	0	640	4	16	4	4	29630	0	10000	10	30038	30122	30085	30132	30038
10024	30084	233	1	1	1	0	88	3143	29548	121	10010	10	10008	10	10000	55	4278670	0	30018	30085	30084	28292	7	28767	10310	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	0	0	0	0	640	4	16	4	4	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  usqadd b0, b0

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28710	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	29629	2	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	10	28760	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	258	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	61	29547	30021	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	30021	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	30021	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	0	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29547	0	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	0	25	10010	10	10000	10	10000	50	4277160	1	30018	3	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	0	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	0	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	3	1	2	3	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	21	61	29547	0	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29547	0	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  usqadd b0, b8
  movi v1.16b, 0
  usqadd b1, b8
  movi v2.16b, 0
  usqadd b2, b8
  movi v3.16b, 0
  usqadd b3, b8
  movi v4.16b, 0
  usqadd b4, b8
  movi v5.16b, 0
  usqadd b5, b8
  movi v6.16b, 0
  usqadd b6, b8
  movi v7.16b, 0
  usqadd b7, b8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	155	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	71	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	865	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	941	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	1018	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	92	1294	80119	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	115	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	333	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	0	1	1	1	10119	16	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20069	155	3	1	0	1	358	25	80010	10	80000	10	80000	50	640000	1	1	20029	20048	20048	3	22	80010	20	80000	20	160000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10054	3	4	2	1	42	22	1	1	1	27	38	20045	33	160000	10	20053	20049	20053	20053	20049
160024	20048	156	1	0	0	1	1634	25	80010	10	80000	10	80000	50	640000	1	1	20029	20048	20049	3	22	80010	20	80000	20	160000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10060	3	5	2	0	36	26	3	2	2	38	39	20049	34	160000	10	20049	20049	20049	20049	20049
160024	20048	155	2	0	0	1	410	25	80010	10	80000	10	80000	50	640000	1	1	20029	20048	20048	3	22	80010	20	80000	20	160000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10061	3	4	1	1	36	22	1	1	1	40	41	20045	33	160000	10	20049	20049	20049	20049	20049
160024	20048	155	1	0	0	1	359	25	80010	10	80000	10	80000	50	640000	1	1	20029	20048	20048	3	22	80010	20	80000	20	160000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10063	3	4	1	0	38	22	1	1	1	38	31	20045	33	160000	10	20049	20049	20049	20049	20049
160024	20048	155	2	0	0	0	381	25	80010	10	80000	10	80000	50	640000	1	1	20029	20052	20048	3	22	80010	20	80000	20	160000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10048	3	4	2	1	39	22	1	1	1	39	39	20049	33	160000	10	20053	20049	20049	20049	20049
160024	20048	156	2	0	0	0	367	25	80010	10	80000	10	80000	50	640000	1	1	20029	20052	20048	3	22	80010	20	80000	20	160000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10061	3	5	1	0	39	22	1	1	1	41	40	20045	33	160000	10	20049	20049	20049	20049	20049
160024	20048	156	1	0	0	0	411	25	80010	10	80000	10	80000	50	640000	1	1	20033	20048	20048	3	22	80010	20	80000	20	160000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10061	6	5	2	0	31	22	1	1	1	40	40	20045	33	160000	10	20049	20049	20049	20049	20049
160024	20052	156	1	0	0	0	375	25	80010	10	80000	10	80000	50	640000	0	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10047	3	4	1	1	23	22	1	1	1	37	39	20045	33	160000	10	20049	20049	20049	20049	20049
160024	20048	155	2	0	0	0	372	25	80010	10	80000	10	80000	50	640000	1	1	20033	20049	20048	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10061	3	5	1	0	31	26	1	2	2	40	40	20045	34	160000	10	20049	20049	20049	20049	20049
160024	20048	155	2	0	0	1	327	25	80010	10	80000	10	80000	50	640000	0	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10063	3	4	1	0	23	22	1	1	1	39	39	20051	33	160000	10	20053	20053	20053	20053	20053

Test 5: throughput

Count: 16

Code:

  usqadd b0, b16
  usqadd b1, b16
  usqadd b2, b16
  usqadd b3, b16
  usqadd b4, b16
  usqadd b5, b16
  usqadd b6, b16
  usqadd b7, b16
  usqadd b8, b16
  usqadd b9, b16
  usqadd b10, b16
  usqadd b11, b16
  usqadd b12, b16
  usqadd b13, b16
  usqadd b14, b16
  usqadd b15, b16

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40049	310	0	27	548	25	160108	100	160008	100	160130	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	24	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	6	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	15	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40145	40040	40040	40040	40040
160204	40039	310	0	513	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	498	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40091	40092	40040
160204	40039	311	0	60	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	311	0	552	114	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	525	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	2	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	225	91	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	2	1	3	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40050	310	0	0	0	80	25	160010	10	160000	10	160000	50	0	1280000	1	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10025	11	5	2	1	34	16	3	2	2	30	31	40036	41	13	160000	10	40040	40040	40040	40040	40040
160024	40039	310	1	0	1	58	25	160010	10	160080	10	160000	50	0	1280000	0	1	5	40020	40039	40039	19996	7	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	1	10022	8	5	1	0	27	16	2	1	1	28	28	40036	41	13	160000	10	40040	40040	40040	40040	40040
160024	40039	310	1	0	1	52	25	160010	10	160000	10	160000	50	0	1280000	0	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10027	6	5	2	1	18	16	3	2	2	27	23	40072	41	13	160000	10	40040	40040	40040	40040	40040
160024	40039	310	1	0	0	58	25	160010	10	160000	10	160000	50	0	1280000	0	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10027	6	5	2	1	21	16	3	2	2	30	20	40061	41	13	160000	10	40040	40040	40040	40040	40040
160024	40039	310	1	0	1	850	25	160010	10	160000	10	160000	50	0	1280000	0	1	0	40202	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10027	6	5	2	1	27	16	3	2	2	22	26	40049	41	13	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	1	63	25	160010	10	160000	10	160000	50	0	1280000	0	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10027	6	5	2	1	27	16	3	2	2	28	27	40185	41	13	160000	10	40040	40040	40040	40092	40040
160024	40039	325	1	0	1	58	25	160010	10	160000	10	160000	50	0	1280000	0	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10025	6	5	2	1	31	16	3	2	2	30	31	40047	41	13	160000	10	40040	40040	40040	40040	40040
160024	40039	321	1	0	1	52	25	160010	10	160000	10	160000	50	0	1280000	0	1	0	40020	40090	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10025	6	5	2	1	28	16	3	2	2	19	30	40058	41	13	160000	10	40040	40040	40040	40040	40040
160024	40039	310	1	0	1	717	25	160010	10	160000	10	160000	50	0	1280000	0	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10025	6	5	2	1	25	16	3	2	2	30	19	40047	41	13	160000	10	40040	40040	40040	40040	40040
160024	40039	310	1	0	1	58	25	160010	10	160000	10	160000	50	0	1280000	0	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10025	6	5	2	1	29	16	3	2	2	30	30	40047	41	13	160000	10	40040	40040	40089	40040	40040

USQADD (scalar, B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations