Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USQADD (scalar, D)

Test 1: uops

Code:

  usqadd d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230000000006125482510001000100039831303018303730372415328951000100020003037303711100110000000003073116122630100030383038303830383038
10043037230000000006125482510001000100039831313018303730372415328951000100020003037303711100110000000000073116112630100030383038303830383038
10043037230000000006125482510001000100039831313018303730372415328951000100020003037303711100110000000000073116112630100030383038303830383038
10043037240000000006125482510001000100039831303018303730372415328951000100020003037303711100110000000000073116112630100030383038303830383038
10043037230000000006125482510001000100039831313018303730372415328951000100020003037303711100110000000100073116112630100030383038303830383038
1004303723000000000612548251000100010003983131301830373037241532895100010002000303730371110011000000000007311625222630100030383038303830383038
10043037240000000006125482510001000100039831313018303730372415328951000100020003037303711100110000000000073116112630100030383038303830383038
10043037230000000006125392510001000100039831313018303730372415328951000100020003037303711100110000000000073116112630100030383038303830383038
10043037230000000006125482510001000100039831303018303730372415328951000100020003037303711100110000000000073116112630100030383038303830383038
10043037240000000006125482510001000100039831313018303730372415328951000100020003037303711100110000000000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  usqadd d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0309191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037233000082295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296770100001003003830038300383003830038
10204300372330000988295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
1020430037233000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296342100001003003830038300383003830038
1020430037233000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
1020430037233000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
1020430037233000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
1020430037233000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
1020430037241000089295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
1020430037233000061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
1020430037233000061295482510100100100001001000058042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372420023625729548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003723200006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000015629548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000053629548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313030018300843003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722400006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  usqadd d0, d0
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372330061295472510100100100001001000050042771601300183003730037282716287411010020010008200200163003730037111020110099100100100001002011171711600296460100001003008530038300383003830038
1020430037233006129547251010010010000100100005004277160030018300373003728271728741101002001000820020016300373003711102011009910010010000100016511171701600296460100001003003830038300383003830038
10204300372320061295472510100100100001001000050042771601300183003730037282716287401010020010008200200163003730037111020110099100100100001000011171701600296460100001003003830038300383003830226
10204300372330061295472510100100100001001000050042771601300183003730037282717287401010020010008200200163003730037111020110099100100100001001011171801600296450100001003003830038300383003830038
10204300372320061295472510100100100001001000050042771601300183003730037282716287401010020010008200200163003730037111020110099100100100001000011171801600296460100001003003830038300383003830038
10204300372330061295472510100100100001001000050042771601300183003730037282716287411010020010008200200163003730037111020110099100100100001001011171701600296450100001003003830038300383003830038
10204300372320061295472510100100100001001000050042771601300183003730037282717287401010020010008200200163003730037111020110099100100100001004011171701600296450100001003003830038300383003830038
10204300372330061295472510100100100001001000050042771600300183003730037282717287401010020010008200200163003730037111020110099100100100001000011171701600296460100001003003830038300383003830038
10204300372330061295472510100100100001001000050042771601300183003730037282717287411010020010008200200163003730037111020110099100100100001002011171801600296450100001003003830038300383003830038
102043003723200856295472510100100100001001000050042771600300183003730037282717287411010020010008200200163003730037111020110099100100100001001011171701600296450100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e5051schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372320000000061295470251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000014406402162229629010000103003830038300383003830038
10024300372330000000061295470251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000012606402162229629010000103003830038300383003830038
10024300372330000000061295470251001010100001010000504277160030054300373003728286328767100102010000202000030037300371110021109101010000100000012606402162229629010000103003830038300383003830038
100243003723300000000612954702510010101000010100005042771600300183003730037282863287671001020100002020252300373003711100211091010100001000000006402162229629010000103003830038300383003830038
10024300372330000000061295470251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000015696402162229629010000103003830038300383008430085
10024300372330001020061295470251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000013806402162229629010000103003830038300383003830038
10024300372330000000061295470251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000011106402162229629010000103003830038300383003830038
10024300372330000000061295470251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000011406402162129629010000103003830038300383003830038
10024300372320000000061295470251001010100001010000504277160030018300373003728286328767100102010000202034430037300371110021109101010000100000012606402162229629010000103003830038300383003830038
100243003723300000000612954702510010101000010100005042771600300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629010000103023530038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  usqadd d0, d8
  movi v1.16b, 0
  usqadd d1, d8
  movi v2.16b, 0
  usqadd d2, d8
  movi v3.16b, 0
  usqadd d3, d8
  movi v4.16b, 0
  usqadd d4, d8
  movi v5.16b, 0
  usqadd d5, d8
  movi v6.16b, 0
  usqadd d6, d8
  movi v7.16b, 0
  usqadd d7, d8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d2d5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042009015600000572580116100800161008002850064019600200452006520065612801282008002820016005620065200651116020110099100100160000100000000111101190001600020062001600001002006620066200662006620066
1602042006515500000292580116100800161008002850064019600200452006520065612801282008002820016005620065200651116020110099100100160000100000000111101190001600020062001600001002006620066200662006620066
1602042006515500000292580116100800161008002850064019610200452006520065612801282008002820016005620065200651116020110099100100160000100000000111101190001600020062001600001002006620066200662006620066
1602042006515500000292580116100800161008002850064019600200452006520065612801282008002820016005620065200651116020110099100100160000100000000111101190001600020062001600001002006620066200662006620066
1602042006515500000712580116100800161008002850064019600200452006520065612801282008002820016005620065200651116020110099100100160000100000000111101190001600020062001600001002006620285200662006620066
1602042006515500000292580116100800161008002850064019600200452006520065612801282008023920016005620065200651116020110099100100160000100000000111101190001600020062001600001002006620066200662006620066
160204201331550001209722580116100800161008002850064019600200452006520065612801282008002820016005620065200651116020110099100100160000100000000111101190001600020062001600001002006620066200662006620066
1602042006515600000732580116100800161008002850064019600200452006520065612801282008002820016005620065200651116020110099100100160000100000000111101190001600020062001600001002006620066200662006620066
1602042006515500000712580116100800161008002850064019610200452006520065612801282008002820016005620065200651116020110099100100160000100000000111101190001600020062001600001002006620066200662006620066
1602042006515500000292580116100800161008002850064019600200452006520065612801282008002820016005620065200651116020110099100100160000100000000111101190001600020062001600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l1i tlb fill (04)181e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200621550000732580010108000010800005064000011020027200462004632280010208000020160000200462004611160021109101016000010000100406221820422171820047300160000102005120051200512005120051
1600242005015602120512580010108000010800005064000001020031200482005232280010208000020160000200502004611160021109101016000010000100446222126422202120049300160000102005320053200522005120053
160024200501550000512580010108000010800005064000001020033200522005032280010208000020160000200522005111160021109101016000010000100466522024422181820049300160000102005120051200512005120051
160024200521550000512580010108000010800005064000011020027200462004632280010208000020160000200462004611160021109101016000010013100466522224322171920049310160000102005120053203502005320133
16002420052155003005125800101080000108000050640000110200272004620046114380010208000020160000200462004811160021109101016000010020100456222066422201720047300160000102004720049200492004720047
160024200461550000452580010108000010800005064000001020031200522005032280010208000020160000200522005211160021109101016000010000100433111820211191820045150160000102005120051200512005120051
160024200501550000512580010108000010800005064000001020033200502005232280010208000020160000200502005011160021109101016000010000100436221724422181820047300160000102005120051200512005120051
160024200501550000512580010108000010800005064000001020031200502005032280010208000020160000200502005011160021109101016000010203100446521824322191820047310160000102005320051200512014420055
160024200501550000512580010108000010800005064000001020033200502005032280010208000020160000200502005011160021109101016000010013100436521624422171720047300160000102005120051202122005120053
160024200501560000512580010108000010800005064000001020031200502005232280010208000020160000200512005011160021109101016000010000100426521724422202220049300160000102005120053200532005320051

Test 5: throughput

Count: 16

Code:

  usqadd d0, d16
  usqadd d1, d16
  usqadd d2, d16
  usqadd d3, d16
  usqadd d4, d16
  usqadd d5, d16
  usqadd d6, d16
  usqadd d7, d16
  usqadd d8, d16
  usqadd d9, d16
  usqadd d10, d16
  usqadd d11, d16
  usqadd d12, d16
  usqadd d13, d16
  usqadd d14, d16
  usqadd d15, d16
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400393100014022516010810016000810016002050012801320140020400394003919977619990160120200160032200320064400394003911160201100991001001600001001011110118001600400361600001004004040040400404004040040
1602044003931000302516010810016000810016002050012801320040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000011110118001600400361600001004004040040400404004040040
1602044003931100582516010810016000810016002050012801320040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000011110118001600400361600001004004040040400404004040040
1602044003931000302516010810016000810016002050012801320040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000011110118001600400361600001004004040040400404004040040
1602044003931000302516010810016000810016002050012801320040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000311110118001600400361600001004004040040400404004040040
1602044003932100302516010810016000810016002050012801321140020400394003919977619990160120200160032200320064400394003911160201100991001001600001000011110118001600400361600001004004040040400404004040040
160204400393100540302516010810016000810016002050012801321140020400394003919977619990160120200160032200320064400394003911160201100991001001600001000011110118001600400361600001004004040040400404004040040
1602044003931000302516010810016000810016002050012801320040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000011110118001600400361600001004004040040400404004040040
1602044003931100302516010810016000810016002050012801320140020400394003919977619990160120200160032200320064400394003911160201100991001001600001000311110118201600400361600001004004040040400404004040040
1602044003931000302516010810016000810016002050012801320040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000011110118001600400361600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)030918191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440040310000004625160010101600001016000050128000011040020400394003919996320019160010201600002032000040039400911116002110910101600001000000000010022311101681181040036305160000104004040040400404004040040
16002440110311000004625160010101600001016000050128000011540020400394003919996320019160010201600002032000040039401041116002110910101600001000000000010022841101643171040036155160000104004040040400404004040040
160024400393100000092251600101016000010160000501280000115400204003940090199963200191600102016000020320000400394008911160021109101016000010000000000100228411016811101040036155160000104004040040400404004040040
16002440039310000005225160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400691116002110910101600001000000000010022841101661110740036155160000104004040040400404004040040
16002440039310000005225160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400631116002110910101600001000000000010022841101681110740036155160000104004040040413094004040040
1600244003931000000462516001010160000101600005012816041154002040039400391999632001916001020160000203200004003940082111600211091010160000100000000001002284181661110940036155160000104004040040401044004040040
16002440039310000904625160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400621116002110910101600001000011247800100228411016822108400363010160000104004040040400404004040040
1600244003931000000462516001010160000101600005012800001154002040039400391999632001916001020160000203200004008940680111600211091010160000100000000001002284181681110740036155160000104004040040400404004040040
16002440039310000004442516001010160000101600005012800001154002040039400391999632001916001020160000203200004003940050111600211091010160000100000000001002284181661110740036155160000104004040040400404004040040
160024400393100000046251600101016000010160000501280000015400204003940039199963200191600102016000020320000400394022211160021109101016000010000000000100228511016422107400363010160000104004040040400404004040040