Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USQADD (vector, 8B)

Test 1: uops

Code:

  usqadd v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303724121032548251000100010003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
100430372401032548251000100010003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
100430372412612548251000100010003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037240612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037230612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
100430372401032548251000100010003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
100430372301242548251000100010003983130301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
100430372315612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038
10043037240612548251000100010003983131301830373037241532895100010002000303730371110011000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  usqadd v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723390061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000001071011611296340100001003003830038300383003830038
10204300372330061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000300071011611296340100001003003830038300383003830038
10204300372330061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000300071011611296340100001003003830038300383003830038
10204300372320061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372330061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
102043003723257254103295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372320061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372330089295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372320061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000000071011611296340100001003003830038300383003830038
10204300372323061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000020071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000006129548251001010100001010000504277313030018030037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313030018030037300372828732876710010201000020200003003730037111002110910101000010010000006402162229630010000103003830038300383003830038
100253003722500000006129548251001010100001010000504277313030018030037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000000117129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243008522500000006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000000006402163329630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003724100000006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000006129548251001010100001010000504277313130018030037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  usqadd v0.8b, v0.8b
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)09l2 tlb miss data (0b)181e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372320000120612954725101001001000010010000500427716003001830037300372827162874110100200100082002001630037300371110201100991001001000010000011171701600296450100001003003830038300383003830038
10204300372330000120612954725101001001000010010000500427716003001830037300372827172874110100200100082002001630037300371110201100991001001000010000011171701600296460100001003003830038300383003830038
10204300842330000006072954725101001001000010010000500427716003001830037300372827162874110100200100082002001630037300371110201100991001001000010000011171701600296460100001003003830038300383003830038
1020430037233000000612954725101001001000010010000500427716003001830037300372827162874110100200100082002001630037300371110201100991001001000010000011171701600296450100001003003830038300383003830038
1020430037233000000612954725101001001000010010000500427040613001830037300372827162874110100200100082002001630037300371110201100991001001000010000011171801600296460100001003003830038300383003830038
102043003723300000014952954725101001001000010010000500427716013001830084300372827172874010100200100082002001630037300371110201100991001001000010000011171801600296460100001003003830038300383003830038
1020430037233000000612954725101001001000010010000500427716003001830037300372827162874110100200100082002001630037300371110201100991001001000010000011171801600296450100001003003830038300383003830038
1020430037233000000612954725101001001000010010000500427716003001830037300372827172874010100200100082002001630037300371110201100991001001000010000011171701600296450100001003003830038300383003830038
1020430037233000000612954725101001001000010010000500427716013001830037300372827162874110100200100082002001630037300371110201100991001001000010000011171701600296450100001003003830038300383003830038
1020430037233000018061295472510100100100001001000050042771601300903003730037282717287401010020010172210200163003730037111020110099100100100001000017411172222422296290100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037233000450061295472510010101000011100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629110000103003830038300383003830038
100243003723300090061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003723300000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003723300000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
1002430037233000000126295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003723300000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
1002430037233000120061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
100243003723300000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629010000103003830038300383003830038
1002430037233000120061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000036402162229629010000103003830038300383003830038
100243003723300000061295472510010101000010100005042771601300183003730037282863287671001020100002020000300373003711100211091010100001000000006402162229629010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  usqadd v0.8b, v8.8b
  movi v1.16b, 0
  usqadd v1.8b, v8.8b
  movi v2.16b, 0
  usqadd v2.8b, v8.8b
  movi v3.16b, 0
  usqadd v3.8b, v8.8b
  movi v4.16b, 0
  usqadd v4.8b, v8.8b
  movi v5.16b, 0
  usqadd v5.8b, v8.8b
  movi v6.16b, 0
  usqadd v6.8b, v8.8b
  movi v7.16b, 0
  usqadd v7.8b, v8.8b
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420088156000000292580116100800161008002850064019602004520065200656128012820080028200160056200652006511160201100991001001600001000001000111101190160200621600001002006620066200662006620066
1602042006515500000031425801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000010001111011901140200621600001002006620066200662006620066
160204200651560000120292580116100800161008002850064019602004520065200656128012820080028200160056200652006511160201100991001001600001000001000111101190160200621600001002006620066200662006620066
1602042006515600000029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000009880111101190160200621600001002006620066200662006620066
16020420065155000000292580116100800161008002850064019602004520065200656128012820080028200160056200652006521160201100991001001600001000001030111101190160200621600001002006620066200662006620066
160204200651550000001152580116100800161008002850064019602004520065200656128012820080028200160056200652006511160201100991001001600001000001030111101190160200621600001002006620066200662006620066
16020420065156000000292580116100800161008002850064019602004520065200656128012820080028200160056200652006511160201100991001001600001000001000111101191160200621600001002006620066200662006620066
16020420065155000000572580116100800161008002850064019602004520065200656128012820080028200160056200652006511160201100991001001600001000000000111101680160200621600001002006620066200662006620066
16020420065155000000292580116100800161008002850064019602004520065200656128012820080028200160056200652006511160201100991001001600001000001400111101190160200621600001002006620066200662006620066
16020420065155000000712580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000001000111101190160200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)181e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420114156000200452780010108000010800005064000011020032200512005132280010208000020160000200512005111160021109101016000010000000100418311925211171320048201160000102005220052200522005220052
16002420063155000000452780010108000010800005064000011520032200512005132280010208000020160000200512005111160021109101016000010000000100428511725211171820048201160000102005220052200522005220052
16002420063156000000452780010108000010800005064000011520032200512005132280010208000020160000200512005111160021109101016000010000000100428511325211191720048201160000102005220052200522005220213
16002420085156000000452780010108000010800005064000011520032200512005132280010208000020160000200522005111160021109101016000010000000100408511725211171220048201160000102005220052200522005220052
160024200661550000004172780010108000010800005064000011520291200602006032280010208000020160000200602005111160021109101016000010000000100418511725211191920048201160000102005220052200522005220052
160024200811550000120452780010108000010800005064000011520032200512005132280010208000020160000200512021211160021109101016000010000000100458511625211161220048201160000102005220052200522005220052
1600242005115500000045278001010800001080000506400001102003220051200513228001020800002016000020060200601116002110910101600001000007710100398111725211111520048201160000102005220052200522005220052
16002420051155000000512780010108000010800005064000000520032200522005132280010208000020160000200512005111160021109101016000010200000100408511725211181920048201160000102005220052200522005220052
16002420051155000000872980010108000010800005064000011520032200512005132280010208000020160000200512005111160021109101016000010000000100398511625422161120048201160000102005220052200522005220052
1600242005115500005550452780010108000010800005064000000520032200512005132280010208000020160000200602006011160021109101016000010000000100403611625211181220048201160000102005220052200612005320061

Test 5: throughput

Count: 16

Code:

  usqadd v0.8b, v16.8b
  usqadd v1.8b, v16.8b
  usqadd v2.8b, v16.8b
  usqadd v3.8b, v16.8b
  usqadd v4.8b, v16.8b
  usqadd v5.8b, v16.8b
  usqadd v6.8b, v16.8b
  usqadd v7.8b, v16.8b
  usqadd v8.8b, v16.8b
  usqadd v9.8b, v16.8b
  usqadd v10.8b, v16.8b
  usqadd v11.8b, v16.8b
  usqadd v12.8b, v16.8b
  usqadd v13.8b, v16.8b
  usqadd v14.8b, v16.8b
  usqadd v15.8b, v16.8b
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044006131100000001117251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000000111101180160040036001600001004004040040400404004040040
160204400393110000000302251601081001600081001600205001280132140020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000030111101180160040036001600001004004040040400404004040040
160204400393100000000298251601081001600081001600205001280132140020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000000111101180160040036001600001004004040040400404004040040
160204400393100000090142251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000000111101180160040036001600001004004040040400404004040040
160204400393110000000401251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000000111101180160040036001600001004004040040400404004040040
160204400393110000000407251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000000111101180160040036001600001004004040040400404004040040
160204400393100000000306251601081001600081001600205001280132140020400394003919977619990160120200160032200320064400394003911160201100991001001600001000001060111101180160040036001600001004004040040400404004040040
16020440039310000000030251601081001600081001600205001281716140631407604082020061712028216145620216178720032313840517407771611602011009910010016000010042300684821111031232043340653101600001004068340869408204081840888
1602044088731711117161848114472622671613691031612701071609195111289640040550407224062020074572031516091020216122920032249640725407201311602011009910010016000010042212469521111034331902340526001600001004041740724406584073240672
160204406653150018121596704570426916146610416117510016131452212894640403534065540718200376520319161415200161220202322666406634073381160201100991001001600001000031047352111103232862240444001600001004004940049400494004940049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244003931000000013725160010101600001016000050128000001040020400394003919996320019160010201600002032000040039400391116002110910101600001000000010024622201622216164003615100160000104004040040400404004040040
1600244007531100000052251600101016000010160000501280000015400204003940039199963200191600102016000020320000400394003911160021109101016000010001000100241152171622216164003630100160000104004040040400404004040040
1600244003931100000046251600101016000010160000501280000015400204003940039199963200191600102016000020320000400394003911160021109101016000010000000100221152101642216104003615100160000104004040040400404004040040
16002440039310000012088251600101016000010160000501280000115400204003940039199963200191600102016000020320000400394003911160021109101016000010000000100241152151642216164003630100160000104004040040400404004040040
160024400393110000005225160010101600001016000050128000011540020400394003919996320019160010201600002032000040039400391116002110910101600001020000010024115216164221694003630100160000104004040040400404004040040
160024400393100000004625160010101600001016000050128000001540020400394003919996320019160010201600002032000040039400391116002110910101600001000000010024114291642217144003630100160000104004040040400404004040040
1600244003931100000014125160010101600001016000050128000001540020400394003919996320019160010201600002032000040039400391116002110910101600001000000010024115291641215154003620190160000104004040040400404004040040
16002440039310000000462516001010160000101600005012800001104002040039400391999632001916001020160000203200004003940039111600211091010160000100000001002231118162111717400362060160000104004040040400404004040040
16002440039310000000522516001010160000101600005012800001104002040039400391999632001916001020160000203200004003940039111600211091010160000100000001002231111162111710400362060160000104004040040400404004040040
160024400393100000004625160010101600001016000050128000011040020400394003919996320019160010201600002032000040039400391116002110910101600001000000010022611181621110174003640120160000104004040040400404004040040