Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

USRA (vector, 4S)

Test 1: uops

Code:

  usra v0.4s, v1.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)031e3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a0a8accfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303724061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383085
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037231284254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303724061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
10043037240505254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303723061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303724061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038
1004303724061254825100010001000398313030183037303724153289510001000200030373037111001100000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  usra v0.4s, v1.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)03080b18191e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a8a9acc2c5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130054300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372240000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003008530038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038
10204300372250000006129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)03191e1f3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10024300372250006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
1002430037225000101295482510010101000010100005042773130300183003730037282872528767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372240006129548251001010100001010000504277313030018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
10024300372250006129548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038
100243003722400042929548251001010100001010000504277313130018300373003728287328767100102010000202000030037300371110021109101010000100006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  usra v0.4s, v0.4s, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)031e3a3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10204300372320097295472510100100100001001000050042771600300183003730037282526287331010020010000200200003003730037111020110099100100100001002801117222242229629100001003003830038300383003830038
1020430037233019729547251010010010000100100005004277160030018300373003728252628733101002001000020020000300373003711102011009910010010000100261117222242229629100001003003830038300383003830038
10204300372330113929547251010010010000100100005004277160030018300373003728252628733101002001000020020000300373003711102011009910010010000100031117222242229629100001003003830038300383003830085
102043003723312197295472510100100100001001000050042771600300183003730037282526287331010020010000200200003003730037111020110099100100100001004001117222242229629100001003003830038300383003830038
1020430037233019729547251010010010000100100005004277160030018300373003728252628733101002001000020020000300373003711102011009910010010000100401117222242229629100001003003830038300383003830038
1020430037233019729547251010010010000100100005004277160030018300373003728252628733101002001000020020000300373003711102011009910010010000100131117222242229629100001003003830038300383003830038
1020430037233019729547251010010010000100100005004277160030018300373003728252628733101002001000020020000300373003711102011009910010010000100131117222242229629100001003003830038300383003830038
10204300372330197295472510100100100001001000050042771600300183003730037282526287331010020010000200200003003730037111020110099100100100001000111181117222242229629100001003003830038300383003830038
10204300372320119829547251010010010000100100005004277160030018300373003728252628733101002001000020020000300373003711102011009910010010000100101117222242229629100001003003830038300383003830038
10204300372330197295473610100100100001001000050042771600300183003730037282717287411010020010008200200163003730037111020110099100100100001003001117180160029645100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire (01)cycle (02)031e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8acbranch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
10024300372330612954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372330612954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
100243008423206312954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372330612954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372330612954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372320612954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372330922954725100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
10024300372320612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037233061295472510010101000010100005042771600300183003730037282863287671001020100002020000300373003711100211091010100001001620640216222962910000103003830038300383003830038
1002430037233061295472510010101000010100005042771600300183003730037282863287671001020100002020000300373003711100211091010100001001560640216222962910000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  usra v0.4s, v8.4s, #3
  movi v1.16b, 0
  usra v1.4s, v8.4s, #3
  movi v2.16b, 0
  usra v2.4s, v8.4s, #3
  movi v3.16b, 0
  usra v3.4s, v8.4s, #3
  movi v4.16b, 0
  usra v4.4s, v8.4s, #3
  movi v5.16b, 0
  usra v5.4s, v8.4s, #3
  movi v6.16b, 0
  usra v6.4s, v8.4s, #3
  movi v7.16b, 0
  usra v7.4s, v8.4s, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire (01)cycle (02)03071e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6escheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a7a8acc5branch mispredict (cb)cdcfd6e0? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204200901550029258011610080016100800285006401961200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011916200621600001002006620066200662006620066
160204200651560029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000101111011916200621600001002006620066200662006620066
160204200651560029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011916200621600001002006620066200662006620066
16020420065155002925801161008001610080028500640196020045200652006561280128200800282001600562006520065111602011009910010016000010000011471111011916200621600001002006620066200662006620066
160204200651550029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000301111011916200621600001002006620066200662006620066
160204200651550029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011916200621600001002013320066200662006620066
160204200651620029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000201111011916200621600001002006620066200662006620066
1602042006515600504258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011916200621600001002006620066200662006620066
160204200651550029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011916200621600001002006620066200662006620066
160204200651550029258011610080016100800285006401960200452006520065612801282008002820016005620065200651116020110099100100160000100000001111011916200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire (01)cycle (02)0304181e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f6061696d6escheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8a9accfd0d2icache miss (d3)d5d6d9dadbddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024200511551004525800101080000108000050640000111020027200462004632280010208000020160000200462004611160021109101016000010100100321632162042211620047030160000102005120051200512005120051
1600242005015500033625800101080000108000050640000011020031200502005032280010208000020160000200502005011160021109101016000010100100371662132422271220043030160000102004720047200512005120051
160024200501550005125800101080000108000050640000111020031200502004632280010208000020160000200502005011160021109101016000010100100291652624412111120047015160000102005120051200512004720047
16002420046156000452580010108000010800005064000001102003120050200503228001020800002016000020046200501116002110910101600001030147510034135172021161120043015160000102004720047200472004720047
1600242004615600068258001010800001080000506400001110200272004620046322800102080000201600002004620046111600211091010160000100015100341351112221161120043015160000102004720047200472004720047
160024200461560004525800101080000108000050640000211020027200462004632280010208000020160000200462005011160021109101016000010100100301362112021111620043015160000102004720047200472004720047
160024200461550094525800101080000108000050640000111020027200462004632280010208000020160000200462004611160021109101016000010100100341351122021111620043015160000102004720047200472004720047
1600242004615600045258001010800001080000506400001110200272004620046322800102080000201600002004620046111600211091010160000101031003413511120211121220043015160000102004720047200472004720047
160024200461550004525800101080000108000050640000111020027200462004632280010208000020160000200462004611160021109101016000010201210035135162121112720043015160000102004720047200472004720052
160024200461550004525800101080000108000050640000111020027200462004632280010208000020160000200462004611160021109101016000010100100291351112021112620044015160000102004820047200472004720047

Test 5: throughput

Count: 16

Code:

  usra v0.4s, v16.4s, #3
  usra v1.4s, v16.4s, #3
  usra v2.4s, v16.4s, #3
  usra v3.4s, v16.4s, #3
  usra v4.4s, v16.4s, #3
  usra v5.4s, v16.4s, #3
  usra v6.4s, v16.4s, #3
  usra v7.4s, v16.4s, #3
  usra v8.4s, v16.4s, #3
  usra v9.4s, v16.4s, #3
  usra v10.4s, v16.4s, #3
  usra v11.4s, v16.4s, #3
  usra v12.4s, v16.4s, #3
  usra v13.4s, v16.4s, #3
  usra v14.4s, v16.4s, #3
  usra v15.4s, v16.4s, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire (01)cycle (02)03080b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2c5branch mispredict (cb)cdcfd2d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044005930000300030251601081001600081001600205001280132140020040039400391997761999016012020016003220032006440039400391116020110099100100160000100000000111101180016004003601600001004004040040400404004040040
1602044003930000003030251601081001600081001600205851280132140020040039400391997761999016012020016003220032006440039400391116020110099100100160000100006000111101180016004003601600001004004040040400404004040040
1602044003929900000030251601081001600081001600205001280132140020040039400391997761999016012020016003220032006440039400391116020110099100100160000100000000111101350016004003601600001004004040040400404004040040
1602044003930000000030251601081001600081001600205001280132140020040039400391997761999016012020016003220032006440039400391116020110099100100160000100000000111101180016004003601600001004004040040400404004040040
1602044003930000000030251601081001600081001600205001280132140020040039400391997761999016012020016003220032006440039400391116020110099100100160000100000000111101180016004003601600001004004040040400404004040040
1602044003930000000030251601081001600081001600205001280132140020040039400391997761999016012020016003220032006440039400391116020110099100100160000100000000111101180016004003601600001004004040040400404004040040
1602044003930000000030251601081001600081001600205001280132140020040039400391997761999016012020016003220032006440039400391116020110099100100160000100000000111101180016004003601600001004004040040400404004040040
1602044003930000000030251601081001600081001600205001280132140020040039400391997761999016012020016023520032006440039400391116020110099100100160000100000000111101180016004003601600001004004040040400404004040040
1602044003930000000030251601081001600081001600205001280132140020040039400391997761999016012020016003220032006440039400391116020110099100100160000100000000111101180016004003601600001004004040040400404004040040
160204400393000000006951721608911001608881021609555111287236140383040507405502007045202541610422001609722003223604050640508111160201100991001001600001002212521301111028802124334040011600001004056640560405104056840537

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire (01)cycle (02)03041e3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f6061696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa8a9accfd0d2icache miss (d3)d5d6d9dadbddinst fetch restart (de)e0eaebec? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16002440039310100220251600101016000010160000501280000100400204003940039199893200121600102016000020320000400394003911160021109101016000010000100261662291632224254003641130160000104004040040400404004040040
160024400393100003352516001010160000101600005012800000110400204003940039199893200121600102016000020320000400394003911160021109101016000010000100241682281632228274003641130160000104004040040400404004040040
160024400393110013122516001010160000101600005012800000110400204003940039199893200121600102016000020320000400394003911160021109101016000010000100261692281632217284003641130160000104004040040400404004040040
160024400393100013342516001010160000101600005012800001110400204003940039199893199971600102016000020320000400394003911160021109101016000010000100221351291621127254003641130160000104004040040400404009940040
160024400393250015882516001010160000101600005012800000110400204003940039199893200121600102016000020320000400394003911160021109101016000010000100241692271632215254003663130160000104004040040400404004040040
160024400393100004802516001010160000101600005012800000110400204003940039199893200121600102016000020320000400394003911160021109101016000010003100261692291632225264003641130160000104004040040400404004040040
160024400393110012022516001010160000101600005012800000110400204003940039199893200121600102016000020320000400394003911160021109101016000010003100261692241632226264003643130160000104004040040400404004040040
160024400393100003082516001010160000101601165012800000110400204003940039199893200121600102016000020320000400394003911160021109101016000010006100241692271632228264003641130160000104004040040400404004040040
160024400393100015702516001010160000101600005012800000110400204003940039199893200121600102016000020320000400394003911160021109101016000010006100261692211632231144003641130160000104004040040400404004040040
160024400393110014342516001010160000101600005012800000110400204003940039199893200121600102016000020320000400394003911160021109101016000010000100261692281632227284003641130160000104004040040400404004040040