Firestorm: USRA (vector, 8H) measurements

Code:

  usra v0.8h, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	0	0	0	0	0	0	2	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	77	4	16	4	4	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	1	0	0	0	0	0	0	0	2	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	77	4	16	4	4	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	1	0	0	0	0	0	0	0	2	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	77	4	16	4	4	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	1	0	0	0	0	0	0	0	2	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	77	4	16	4	4	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	1	0	0	0	0	0	0	0	2	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	77	4	16	4	4	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	1	0	0	0	0	0	0	0	2	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	77	4	16	4	4	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	1	0	0	0	0	0	0	0	2	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	77	4	16	4	4	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	1	0	0	0	0	0	0	0	2	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	84	0	77	4	16	4	4	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	1	0	0	0	0	0	0	0	2	124	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	77	4	16	4	4	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	1	0	0	0	0	0	0	0	2	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	1	0	63	0	77	4	16	4	4	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  usra v0.8h, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	241	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10202	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	253	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	89	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	12	117	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	17	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	61	29548	25	10125	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28764	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	232	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20998	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	245	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	6	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	48	15	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	103	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	21334	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  usra v0.8h, v0.8h, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	233	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	2	1	10201	100	99	100	100	10000	100	0	0	0	0	2	1	1	1	717	1	16	0	0	29646	0	10000	100	30038	30038	30086	30038	30038
10204	30037	233	0	0	0	0	0	61	29547	25	10112	100	10016	100	10000	500	4277160	1	30018	30037	30037	28275	6	28741	10254	200	10008	200	20016	30086	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30085	30038	30038	30038	30038
10204	30037	233	0	0	0	88	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30054	30037	30037	28271	11	28741	10100	200	10008	200	20358	30037	30037	1	1	10201	100	99	100	100	10000	100	4	0	0	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	132	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	12	28741	10100	200	10008	200	20348	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	220	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	2	1	10201	100	99	100	100	10000	100	0	0	0	3	0	1	1	1	718	0	24	0	0	29684	0	10000	100	30086	30038	30038	30038	30038
10204	30037	232	0	0	9	0	0	124	29547	25	10100	100	10000	100	10000	500	4277160	1	30090	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	1856	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30179	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	699	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	12	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30086	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	26	0	0	29645	0	10000	100	30038	30038	30087	30038	30038
10204	30037	233	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	5590	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	232	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	400	29547	25	10010	10	10000	10	10000	50	4281216	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	1	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	0	30037	30037	28286	7	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	2	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	18	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	0	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	0	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  usra v0.8h, v8.8h, #3
  movi v1.16b, 0
  usra v1.8h, v8.8h, #3
  movi v2.16b, 0
  usra v2.8h, v8.8h, #3
  movi v3.16b, 0
  usra v3.8h, v8.8h, #3
  movi v4.16b, 0
  usra v4.8h, v8.8h, #3
  movi v5.16b, 0
  usra v5.8h, v8.8h, #3
  movi v6.16b, 0
  usra v6.8h, v8.8h, #3
  movi v7.16b, 0
  usra v7.8h, v8.8h, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2509

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	155	0	71	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	75	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	75	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10171	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	171	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	63	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	78	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	105	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20054	155	2	0	0	1	0	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	0	10037	8	2	1	14	20	2	1	1	16	15	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	156	4	0	0	1	0	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20050	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	0	10039	8	2	1	17	20	2	1	1	14	16	20044	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	156	1	0	0	0	0	0	0	3	0	0	45	25	80010	10	80080	10	80000	50	640000	1	1	5	20027	20047	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	0	10039	8	2	1	16	20	2	1	1	14	16	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	155	2	0	0	1	0	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	0	10040	8	2	1	14	20	2	1	1	14	16	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	155	1	0	0	0	0	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	0	10036	8	2	1	15	20	2	1	1	16	14	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	155	0	0	0	0	0	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20029	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	0	10038	8	2	1	15	20	2	1	1	14	17	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	155	0	0	0	0	0	0	0	3	0	0	73	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	0	10038	8	2	1	16	20	2	1	1	16	13	20043	15	0	0	160000	10	20047	20047	20048	20047	20047
160024	20046	155	0	0	0	0	0	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20028	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	0	10037	8	2	1	14	20	2	1	1	15	16	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	155	0	0	0	0	0	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	0	10038	8	2	1	15	20	2	1	1	17	15	20043	15	0	0	160000	10	20047	20047	20047	20047	20047
160024	20046	155	0	0	0	0	0	0	0	0	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	0	10038	8	2	1	14	20	2	1	1	17	15	20043	15	0	0	160000	10	20047	20047	20047	20047	20047

Test 5: throughput

Count: 16

Code:

  usra v0.8h, v16.8h, #3
  usra v1.8h, v16.8h, #3
  usra v2.8h, v16.8h, #3
  usra v3.8h, v16.8h, #3
  usra v4.8h, v16.8h, #3
  usra v5.8h, v16.8h, #3
  usra v6.8h, v16.8h, #3
  usra v7.8h, v16.8h, #3
  usra v8.8h, v16.8h, #3
  usra v9.8h, v16.8h, #3
  usra v10.8h, v16.8h, #3
  usra v11.8h, v16.8h, #3
  usra v12.8h, v16.8h, #3
  usra v13.8h, v16.8h, #3
  usra v14.8h, v16.8h, #3
  usra v15.8h, v16.8h, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40039	311	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40036	0	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	0	0	0	0	0	72	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	0	16	1	1	40639	0	160000	100	40570	40872	40823	40827	40772
160204	40822	316	1	16	15	2112	1320	1	7302	324	161191	103	161667	100	161747	500	1293026	1	40706	40619	40983	20127	80	20473	161765	200	161689	202	323362	40616	40814	16	1	160201	100	99	100	100	160000	100	2	2	3	0	0	8005	2	2	2	10351	2	206	1	1	40695	1	160000	100	40979	40870	40934	40522	40623
160204	40927	315	0	13	13	1068	1144	0	4782	174	161470	104	161171	100	161321	500	1290516	1	40551	40727	40675	20081	63	20345	160820	200	161322	200	322684	40718	40705	14	1	160201	100	99	100	100	160000	100	0	0	2	0	4	3530	1	1	1	10342	2	179	3	2	40366	0	160000	100	40716	40727	40717	40728	40726
160204	40689	316	0	8	10	1062	528	0	64	26	160116	100	160016	100	160028	500	1280196	0	40029	40048	40049	19976	9	19986	160128	200	160038	200	320076	40049	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10128	1	23	1	1	40046	0	160000	100	40049	40049	40049	40050	40050
160204	40048	311	0	0	0	0	0	0	64	26	160116	100	160016	100	160028	500	1280196	0	40029	40048	40048	19976	10	19986	160128	200	160038	200	320076	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10128	1	23	1	1	40045	0	160000	100	40050	40050	40050	40049	40050
160204	40048	310	0	0	0	0	0	0	159	26	160116	100	160016	100	160028	500	1280196	0	40029	40048	40049	19976	9	19986	160128	200	160038	200	320076	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	0	2	2	2	10145	1	23	1	1	40045	0	160000	100	40049	40049	40049	40050	40049
160204	40048	310	0	0	0	0	0	0	64	27	160116	100	160016	100	160028	500	1280196	0	40029	40049	40048	19976	9	19986	160128	200	160038	200	320076	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10129	1	23	1	1	40045	0	160000	100	40050	40049	40049	40049	40049
160204	40048	311	0	0	0	0	0	0	64	26	160116	100	160016	100	160028	500	1280196	0	40029	40049	40049	19976	9	19986	160128	200	160038	200	320076	40048	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	2	2	2	10128	1	23	1	1	40045	0	160000	100	40050	40050	40050	40050	40050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	b8	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40050	311	1	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	68	0	0	0	0	0	0	10022	3	1	1	0	22	16	2	1	1	17	17	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	76	0	0	0	0	0	0	10022	3	1	1	0	11	16	1	1	1	14	17	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	322	1	0	46	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	12	0	0	0	0	10022	3	1	1	0	16	16	2	1	1	17	17	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	711	25	160010	10	160388	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	48	0	0	0	0	0	0	10022	3	1	1	0	15	16	1	1	1	20	14	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	279	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160022	10	9	10	10	160000	10	0	0	39	0	0	0	0	0	0	10022	3	1	1	0	15	16	1	1	1	18	16	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	311	0	0	67	89	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	8	0	6	0	0	0	0	10022	3	1	1	0	15	16	1	1	1	17	17	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	403	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	62	0	0	0	0	0	0	10022	3	1	1	0	14	16	1	1	1	19	17	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	311	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	36	0	0	0	0	0	0	10022	3	1	1	0	16	16	2	1	1	20	18	40036	16	5	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	46	25	160010	10	160395	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	18	0	0	0	0	10022	3	1	1	0	18	16	2	1	1	16	16	40036	16	5	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	7	0	3	0	0	0	0	10022	3	1	1	0	17	16	2	1	1	17	16	40036	15	5	160000	10	40040	40040	40040	40040	40040

USRA (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations