Firestorm: USRA (vector, D) measurements

Code:

  usra d0, d1, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	50	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	0	0	0	0	0	0	61	2548	0	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	3	0	6	73	3	16	3	3	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	0	0	0	0	0	61	2548	0	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	1	0	0	57	73	3	16	3	3	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	0	0	0	0	0	632	2548	0	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	0	0	0	0	0	0	61	2548	0	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	0	0	0	0	0	89	2548	0	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	0	0	0	0	0	0	251	2548	0	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	0	0	0	0	0	0	84	2548	0	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	0	0	0	0	0	0	61	2548	0	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	0	0	0	0	0	0	61	2548	0	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	0	73	3	16	3	3	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	0	0	0	0	0	0	61	2548	0	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	0	0	3	73	3	16	3	3	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  usra d0, d1, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	232	12	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	107	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	103	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	117	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	233	0	0	0	0	0	0	719	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30083	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	9	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  usra d0, d0, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	233	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	1	1	1	717	1	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28741	10100	200	10000	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	24	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30084	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	42	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	241	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	0	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	0	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	232	0	0	96	684	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	5	4	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	30	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	5	16	5	5	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	81	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	5	16	5	5	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	15	103	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	6	16	5	6	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	24	103	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	6	16	6	5	29629	0	10000	10	30038	30038	30085	30086	30038
10024	30037	232	0	0	0	61	29538	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	6	16	6	5	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	0	103	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	6	16	6	5	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	435	61	29547	25	10018	10	10008	10	10000	50	4279864	1	30018	30132	30133	28291	3	28767	10010	20	10324	20	20648	30133	30133	2	1	10021	10	9	10	10	10000	10	0	4	5390	0	640	7	16	6	4	29629	0	10000	10	30085	30038	30038	30038	30038
10024	30037	233	0	0	81	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	2	1	10021	10	9	10	10	10000	10	0	0	0	0	640	6	16	5	6	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	30	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	5	16	6	5	29629	0	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  usra d0, d8, #3
  movi v1.16b, 0
  usra d1, d8, #3
  movi v2.16b, 0
  usra d2, d8, #3
  movi v3.16b, 0
  usra d3, d8, #3
  movi v4.16b, 0
  usra d4, d8, #3
  movi v5.16b, 0
  usra d5, d8, #3
  movi v6.16b, 0
  usra d6, d8, #3
  movi v7.16b, 0
  usra d7, d8, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	155	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	0	20065	20065	6	12	80551	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	52	2	6	1	1	1	10119	0	1	16	0	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	29	25	80116	104	80019	100	80031	500	640220	0	20056	0	20078	20077	9	12	80131	200	80031	200	160062	20077	20077	1	1	160201	100	99	100	100	160000	100	0	0	162	2	2	2	10131	0	1	23	0	1	1	20075	160000	100	20078	20079	20079	20079	20078
160204	20077	155	0	65	29	80119	100	80019	100	80031	500	640220	1	20056	0	20078	20077	9	12	80131	200	80031	200	160062	20077	20078	1	1	160201	100	99	100	100	160000	100	0	0	6	2	2	2	10130	0	1	23	0	1	1	20074	160000	100	20078	20078	20078	20078	20078
160204	20078	156	0	65	29	80119	100	80019	100	80031	500	640220	1	20056	0	20078	20077	9	12	80131	200	80031	200	160062	20077	20077	1	1	160201	100	99	100	100	160000	100	0	0	3	2	2	2	10130	0	1	23	0	1	1	20074	160000	100	20079	20079	20078	20078	20078
160204	20078	156	0	65	30	80119	100	80019	100	80031	500	640220	1	20056	0	20077	20077	9	12	80131	200	80031	200	160062	20078	20077	1	1	160201	100	99	100	100	160000	100	0	0	0	2	2	2	10130	0	1	23	0	1	1	20074	160000	100	20078	20079	20079	20078	20078
160204	20077	156	0	65	29	80119	100	80019	100	80031	500	640220	0	20056	0	20078	20077	9	12	80131	200	80031	200	160062	20078	20078	1	1	160201	100	99	100	100	160000	100	0	0	0	2	2	2	10131	0	1	23	0	1	1	20075	160000	100	20078	20078	20078	20078	20078
160204	20077	155	153	65	29	80119	100	80019	100	80031	500	640220	1	20056	0	20078	20077	9	12	80131	200	80031	200	160062	20077	20077	4	1	160201	100	99	100	100	160000	100	30	0	0	2	2	2	10130	0	1	23	24	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	44	0	0	1	1	1	10119	0	0	16	0	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	50	0	3	1	1	1	10119	0	0	16	0	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	47	0	0	1	1	1	10119	0	0	16	0	0	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20071	155	2	1	0	0	0	0	45	27	80010	10	80000	10	80000	50	640000	1	1	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	12	0	10044	3	2	1	23	25	4	2	2	19	19	20058	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	155	1	1	0	0	0	0	598	29	80010	10	80000	10	80000	50	640000	0	1	20041	20060	20060	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10046	6	2	2	22	34	4	2	2	18	18	20058	40	2	160000	10	20063	20061	20061	20061	20062
160024	20060	161	0	1	0	0	0	0	929	29	80010	10	80000	10	80000	50	640000	0	1	20041	20060	20060	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	4	0	0	0	0	10044	6	2	2	17	130	4	2	2	21	20	20057	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	156	1	1	0	0	0	0	932	29	80010	10	80000	10	80000	50	640000	0	1	20041	20060	20060	3	22	80010	20	80000	20	160630	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10045	6	2	2	17	34	4	2	2	19	19	20057	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	155	2	1	0	0	0	0	51	29	80010	10	80000	10	80000	50	640000	0	1	20041	20060	20060	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10045	6	2	2	20	34	4	2	2	19	18	20057	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	156	2	1	0	0	0	0	51	29	80010	10	80000	10	80000	50	640000	0	1	20041	20060	20060	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10040	6	2	2	18	34	4	2	2	16	18	20057	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	156	1	2	0	0	0	0	51	29	80010	10	80000	10	80000	50	640000	1	1	20041	20060	20060	3	22	80010	20	80000	20	160416	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10045	6	2	2	18	34	4	2	2	18	20	20058	40	2	160000	10	20061	20061	20061	20061	20061
160024	20051	155	1	1	0	0	0	0	235	27	80010	10	80000	10	80000	50	640000	0	1	20041	20060	20060	3	22	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	3	0	10040	3	1	1	19	25	2	1	1	19	18	20048	20	1	160000	10	20052	20052	20052	20052	20052
160024	20060	155	1	2	0	0	0	0	57	29	80010	10	80000	10	80000	50	640000	0	1	20041	20060	20060	3	22	80010	20	80000	20	160634	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	3	0	10044	3	2	2	20	34	4	2	2	21	19	20057	40	2	160000	10	20061	20061	20061	20061	20061
160024	20060	156	2	1	0	0	0	0	57	29	80010	10	80000	10	80000	50	640000	0	1	20041	20060	20060	3	109	80010	20	80000	20	160000	20060	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	0	9	0	10042	6	2	2	17	34	4	2	2	20	18	20057	40	2	160000	10	20061	20061	20061	20061	20061

Test 5: throughput

Count: 16

Code:

  usra d0, d16, #3
  usra d1, d16, #3
  usra d2, d16, #3
  usra d3, d16, #3
  usra d4, d16, #3
  usra d5, d16, #3
  usra d6, d16, #3
  usra d7, d16, #3
  usra d8, d16, #3
  usra d9, d16, #3
  usra d10, d16, #3
  usra d11, d16, #3
  usra d12, d16, #3
  usra d13, d16, #3
  usra d14, d16, #3
  usra d15, d16, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40058	300	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19986	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40089	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40050	311	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160138	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	1	1	24	16	4	1	1	20	20	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	0	0	987	25	160010	10	160000	10	160000	50	1280000	1	0	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	1	1	22	16	2	1	2	21	20	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	0	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	1	1	20	16	2	1	1	21	20	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	0	0	46	25	160107	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	4	1	22	16	2	1	1	22	22	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	12	0	46	25	160010	10	160000	10	160000	50	1280000	1	0	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	1	1	23	16	2	1	1	21	21	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	12	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	4	1	21	16	2	1	1	22	21	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	311	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	0	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	5	3	15	16	2	1	1	21	22	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	311	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	4	1	22	16	2	1	1	22	22	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	15	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	4	1	23	16	2	1	1	21	23	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	6	0	46	25	160010	10	160000	10	160000	50	1280000	1	0	5	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	168	0	10022	8	4	1	23	16	2	1	1	22	14	40036	15	5	160000	10	40040	40040	40040	40040	40040

USRA (vector, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations