Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USUBL2 (vector, 4S)

Test 1: uops

Code:

  usubl2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203716061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037211001100000073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100020073116111787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  usubl2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715500000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000000071011611197910100001002003820038200862003820038
1020420037156000000103196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000000071011611197910100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000000071011611197910100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000000071011611197910100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000003000071011611197910100001002003820038200382003820038
102042003715500000061196872510100100100001241000050028476801200182003720037184296187411010020010008200200162003720037111020110099100100100001000000000011171801600198010100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000000071011611197910100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000000071011611197910100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000000071011611197910100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371550061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371550061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371550061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371560061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820085
100242003715500232196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371560061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221984610000102003820038200382003820038
10024200371550061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371550061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371550061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371550061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  usubl2 v0.4s, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371550000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371550000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000003071011611197910100001002003820038200382003820038
10204200371550000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715500000001311968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000051071011611197910100001002003820038200382003820038
10204200371550000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371550000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715500000003461968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715500000001031968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371550000000821968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037155000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006403162319785010000102003820038200382003820038
100242003715504454044033621964311510071121006016109127128540950201622022820275184573018860107722110817202190220275202627110021109101010000100022296887274652319984410000102027720275202732027620325
100242031915715567244033721961011410076131006012107606028540190202342027220276184602618853106252410819242194020276202756110021109101010000100001036402162219785010000102003820038200382003820038
100242003715500000136719687821004816100361410760602847680120018200372003718444318767100102010668222131420225200841110021109101010000100001458887452403219970310000102027620278202762027320273
100242027615700002641073196876210038101003615106086628528120201982022920277184593187671001020106642221332202872022651100211091010100001020002667883654219785310000102041720132201352003820132
1002420419163055660352248019610155101101010000101000088286051012027020226200371846230188971077222113172020000200372032451100211091010100001002000178557942162219785010000102003820038200382003820038
10024200371550000071196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000070066402162219785010000102003820038200382003820038
10024200371550000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000082036402162219785010000102003820038200382003820038
10024200371560000072619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000036402162219785010000102003820038200382003820038
1002420037155000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000036402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  usubl2 v0.4s, v8.8h, v9.8h
  usubl2 v1.4s, v8.8h, v9.8h
  usubl2 v2.4s, v8.8h, v9.8h
  usubl2 v3.4s, v8.8h, v9.8h
  usubl2 v4.4s, v8.8h, v9.8h
  usubl2 v5.4s, v8.8h, v9.8h
  usubl2 v6.4s, v8.8h, v9.8h
  usubl2 v7.4s, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815509402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051102161120035800001002003920039200392003920039
802042003815500822580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
8020420038155012402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161220035800001002003920039200392003920039
802042003815500402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101162120035800001002003920039200392003920039
8020420038156012402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100100051101161120035800001002003920039200392003920039
8020420038155007682580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815500822580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100100051101163120035800001002003920039200392003920039
802042003816000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815500402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
8020420038155012402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391560051425800101080000108000050640000020019200382003899963100188011820800002016000020038200381180021109101080000100050200216222003580000102003920039200392003920039
8002420038155003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050200216222003580000102003920039200392003920039
8002420038155003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100350200216222003580000102003920039200392003920039
8002420038155003925800101080000108000050640000120067200382003899963100188001020800002016000020038200381180021109101080000100050200316232003580000102003920039200392003920039
8002420038156003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100350200216232003580000102003920039200392003920039
80024200381550339258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001013050200316232003580000102003920039200392003920039
8002420038155003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050200216222003580000102003920039200392003920039
8002420038155006125800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000103050200216222003580000102003920039200392003920039
8002420038155003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100350200216222003580000102003920039200392003920039
8002420038161003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050200216222003580000102003920039200392003920039