Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USUBL2 (vector, 8H)

Test 1: uops

Code:

  usubl2 v0.8h, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716006116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020852038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037150061168725100010001000264680020182037203715723189510001000200020372037111001100001573216221787100020382038203820382038
10042037150061168725100010001000264680020182037203715723189510001000200020372037111001100016073216221787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110001373216221787100020382038203820382038
100420371603398916872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000373216221787100020382038203820382038
1004203716006116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  usubl2 v0.8h, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371550000000103196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000710116111979100100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000710116111979100100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000710116111979100100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800200182003720084184253187451010020010000200200002003720037111020110099100100100001000000000710116111979100100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000710116111979100100001002003820038200382003820038
10204200371550000000124196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000710116111979101100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000710116111979100100001002003820038200382003820038
1020420037155000000082196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000001710116111979100100001002003820038200382003820038
1020420085155000000085196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000710116111979100100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000710116111985700100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715500131196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001022118606402162219785010000102003820038200382003820038
10024200371500012619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785210000102022820038200382003820038
1002420037150036119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150006119643251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037201107119687251001012100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219877010000102003820038200382003820038
100242003715000145196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001052006402162219785010000102003820038200382003820038
100242003715000159019687251001210100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150096119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000101006402162219785010000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  usubl2 v0.8h, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371560000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071021611197910100001002003820038200382003820038
10204200371610000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371560000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715500000251196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001001000071011611197910100001002003820038200382003820038
102042003715500000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000300710116111979121100001002003820038200382003820038
102042003715500042922061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371550000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000030071011611197910100001002003820038200382003820038
10204200371550000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371550000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
10204200371550000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000030071021611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037155000000017419687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001001006402162219785010000102003820038200382003820038
100242003715500000006119687251001210100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715500000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715500000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382008520038
100242003715500000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715500000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715500000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715500000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715500000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162419785010000102003820038200382003820038
100242003715600000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  usubl2 v0.8h, v8.16b, v9.16b
  usubl2 v1.8h, v8.16b, v9.16b
  usubl2 v2.8h, v8.16b, v9.16b
  usubl2 v3.8h, v8.16b, v9.16b
  usubl2 v4.8h, v8.16b, v9.16b
  usubl2 v5.8h, v8.16b, v9.16b
  usubl2 v6.8h, v8.16b, v9.16b
  usubl2 v7.8h, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815500154025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051102161120035800001002003920039200392003920039
802042003815600274025801001008000010080000500640000020057200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920090
80204200381550004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381550006825801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381550006125801001008000010080000571640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815600244025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381610094025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381551004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038218020110099100100800001000351101161120035800001002003920039200392003920039
802042003815500424025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000351101161120035800001002003920039200392003920039
80204200381550034025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)d9ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471561021039258001010800001080000506400000200192003820038999631001880010208000020160000201392019211800211091010800001000000502001765026212003580000102003920039200392003920039
8002420038155000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000502002416012232003580000102003920039200392003920039
8002420038155000081258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000502002416015232003580000102003920039200392003920039
8002420038155000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000502002016015252003580000102003920039200392003920039
80024200381550012039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000502002516027262003580000102003920039200392003920039
8002420038155000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000502002253022272003580000102003920039200392003920039
8002420038156000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000300502002716027262003580000102003920039200392003920039
800242003815600001052580010108000010800005064000002001920038200381000531001880010208000020160000200892003811800211091010800001000000502002216026272003580000102003920039200892003920039
8002420038155000039258001010800001080000506400000200652003820038999681001880010208000020160000200382003811800211091010800001000000502001216026142003580000102003920039200392003920039
8002420038155000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000502001316026202003580000102003920039200392003920039