Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USUBL (vector, 4S)

Test 1: uops

Code:

  usubl v0.4s, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)0309l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715000061168725100010121000264680201820852037157261895100010002000203720372110011000310073416111787100020382038203820382038
1004208415100661168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
1004203716000061168725100010001000264680201820372037157231895100010002000203720371110011000001073116111787100020382038203820382038
1004203716000061168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
1004203715000061168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
1004203716000061168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
1004203716000061168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150000198168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
1004203716000075168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
100420371600016561168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  usubl v0.4s, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715506119687251010010010000100100005002847680200182003720037184296187401010020010008200200162003720037111020110099100100100001000011171701600198010100001002003820038200382003820038
10204200371550103196872510100100100001001000050028476802001820037200371842971874010100200100082002001620037200371110201100991001001000010034311171701600198010100001002003820038200382003820038
102042003715606119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001001000071011611197910100001002003820038200382003820038
1020420037155080819687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200852003820038
1020420037155061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010005410071011611197910100001002003820038200382003820038
1020420037155061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010005400071011611197910100001002003820038200382003820038
102042003715596119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001001713200071011611197910100001002003820038200382003820038
102042003715506119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001001000071011611197910100001002003820038200382003820038
102042003715506119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002008520038200382003820038
102042003715506119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001003640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010093640216221978510000102003820038200382003820038
100242003715002461196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371504061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371600061196872510010101000010101505028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001019640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001003640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  usubl v0.4s, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000002000710011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000003000710011611197910100001002003820038200382003820038
10204200371550000000103196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000003000735011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000001030710011621197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037211020110099100100100001000000030710011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001002200000710011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028514901200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000710011611197910100001002003820038200382003820038
1020420037156000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000030710011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000710011611197910100001002003820038200382003820038
102042003715500000001031968725101001001000010010000500284768002001820037200371842218187451010020010000200200002003720037111020110099100100100001000000000710011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715510000001031968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000036402162219785010000102003820038200382003820038
10024200371550000000241519643138100751210060131064470285409502020020226203201846131876710010201000020200002003720037211002110910101000010001066402162219785010000102003820038200382003820038
100242003715501000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100002696402162219785010000102003820038200382003820038
100242003715500155669440611968725100221010000121060865285281202001820037200371844431876710010201000020200002003720037111002110910101000010000036602162219785310000102003820038200382003820038
100242003715500000035231321964310410077131006014106086628540950201622022520131184572518848107742210826202132020276202756110021109101010000104200158657893813220065310000102037120369203232041820275
100242041315802077927704473619610175101101210085151106460284768002001820037200371844431876710010201000020206622027520371811002110910101000010000136402162219785010000102003820038200382003820038
10024200371560000000661219687137100611710072141091288285152902023420322203231844431876710010201000022200002013220180411002110910101000010000106402162219785010000102003820038200382003820038
1002420037155000001803641968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000606402162219785010000102003820038200382003820038
10024200371550000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000406402162219785010000102003820038200382003820038
10024200371550000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000106402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  usubl v0.4s, v8.4h, v9.4h
  usubl v1.4s, v8.4h, v9.4h
  usubl v2.4s, v8.4h, v9.4h
  usubl v3.4s, v8.4h, v9.4h
  usubl v4.4s, v8.4h, v9.4h
  usubl v5.4s, v8.4h, v9.4h
  usubl v6.4s, v8.4h, v9.4h
  usubl v7.4s, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f243f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200571550000000040258010010080000100800005006400001020019200382003899733999680100200800002001600002003820038118020110099100100800001000000005110002161120035014800001002003920039200392003920039
8020420038155000000004025801001008000010080000500640000102001920038200389973399968010020080000200160000200382003811802011009910010080000100000103511000116112003500800001002003920039200392003920039
8020420038155000000004025801001008000010080000500640000102001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511000116112003500800001002003920039200392003920039
8020420038156000000004025801001008000010080000500640000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000003511000116112003500800001002003920039200392003920039
8020420038155000000004025801001008000010080096615640000102001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511000116112003500800001002003920039200392003920039
8020420038155000000004025801001008000010080000500640000102001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511000116112003500800001002003920039200392003920039
8020420038155000000004025801001008000010080000500640000102001920038200389973399968010020080000200160000200882003811802011009910010080000100000000511000116112003500800001002003920039200392003920039
8020420038155000000004025801001008000010080000500640000102001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511000116112003500800001002003920039200392003920039
8020420038155000000004025801001008000010080000500640000102001920038200389973399968010020080000200160000200382003811802011009910010080000100000100511000116112003500800001002003920039200392003920039
80204200381550000000017225801001008000010080000500640000102001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511000116112003500800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815600003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000502004164320035080000102003920039200392003920039
800242003815500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000502004163520035080000102003920039200392003920039
800242003815500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000502004164420035080000102003920039200392003920039
800242003815500003960801041080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000502003163420035080000102003920039200392003920039
800242003815500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000502004164320035080000102003920039200392003920039
800242003815500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000502004164420035080000102003920039200392003920039
800242003815500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000502004163420035080000102003920039200392003920039
800242003815600003925800101080000108000050640000020019200382003899963100188001020800002016000020038200871180021109101080000100000502004164420035080000102009120039200392003920039
800242003815500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000502003164320035080000102003920039200392003920039
800242003815500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000502004164420035080000102003920039200392003920039