Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USUBL (vector, 8H)

Test 1: uops

Code:

  usubl v0.8h, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716611687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203716611687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203716611687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715611687251000100010002646802022203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203716611687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037151561687251000100010002646802018203720371572318951000100020002037203711100110000073216221855100020382038203820382038
1004203716611687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037161051687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715611687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203716611687251000100010002646802018203720371572318951000100020002037203711100110000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  usubl v0.8h, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715511206119687251010010010000100100005002847680020018200372003718422318745101252001000020020000200372003711102011009910010010000100000071021721197910100001002003820038200382003820038
102042003715503906119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037155060061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000003710117111979125100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715504506119687251010010010000100100005002847680020018200372003718422318745101252001000020020000200372003711102011009910010010000100000071211611197910100001002003820038200382003820038
102042003715503606119687251010010010000100100006262847680020018200372003718422318745101252001000020020000200372003711102011009910010010000100020071211611197910100001002003820038200382003820038
1020420037155054061196872510100100100001001000050028476800200182003720037184223187441010020010000200200002003720037111020110099100100100001000000710116111979125100001002003820038200382003820038
102042003715603906119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715504506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100002071011611197910100001002003820038200382003820038
1020420037155136308919687251012510010000125100006262847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037156000611968725100101010000101000050284768012001802003720037184440318767100102010000202000020037200371110021109101010000100006404163319785010000102003820038200382003820038
1002420037155000611968725100101010000101000050284768002001802003720037184440318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038
1002420037155000611968725100101010000101000050284768002005402003720037184440318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038
1002420037155000611968725100101010000101000050284768002001802003720037184440318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038
1002420037155000611968725100101010000101000050284768002001802003720037184440318767100102010000202000020037200371110021109101010000100106403163319785010000102003820038200382003820038
1002420037155000611968725100101010000101000050284768002001802003720037184440318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038
1002420037156000611968725100101010000101000050284768012001802003720037184440318767100102010000202000020037200371110021109101010000100106403163319785010000102003820038200382003820038
1002420037155000611968725100101010000101000050284768002001802003720037184440318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038
1002420037155000611968725100101010000101000050284768002001802003720037184440318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038
1002420037155000611968725100101010000101000050284768012001802003720037184440318767100102010000202000020037200371110021109101010000100006403163319785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  usubl v0.8h, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155002461196872510100100100001001000050028476800200182003720037184228187631010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037156000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010002471011611197910100001002003820038200382003820038
1020420037155000567196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715600061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001001071011611197910100001002003820038200382003820038
1020420037155002461196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715600061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037211020110099100100100001000071011611197910100001002003820038200382003820038
102042003715500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715500273103196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037155156119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640416221978510000102003820038200382003820038
10024200371552946119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371553366119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037155366119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371553816119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100020950640216221978510000102003820038200382003820038
10024200371554146119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371553096119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100030640216221978510000102003820038200382003820038
10024200371553308219687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371563546119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371553906119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100030640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  usubl v0.8h, v8.8b, v9.8b
  usubl v1.8h, v8.8b, v9.8b
  usubl v2.8h, v8.8b, v9.8b
  usubl v3.8h, v8.8b, v9.8b
  usubl v4.8h, v8.8b, v9.8b
  usubl v5.8h, v8.8b, v9.8b
  usubl v6.8h, v8.8b, v9.8b
  usubl v7.8h, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060155000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511031612200350800001002003920039200392003920039
8020420038155000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038155000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038155000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100001000511011611200350800001002003920039200392003920039
8020420038155000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038155000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003821802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038155000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038155000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038161000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038155000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)dadbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915500392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000502071600992003580000102003920039200392003920039
80024200381550018032580010108000010800005064076411200192003820038999631001880010208000020160000200382003811800211091010800001000502091600952003580000102003920039200392003920039
80024200381550055625800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010005020131600492003580000102003920039200392003920039
8002420038155003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010005020416001392003580000102003920039200392003920039
80024200381550039258001010800001080000506400000120019200382003899963100188001020800002016000020038200381180021109101080000100050201316005132003580000102003920039200392003920039
800242003815500392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000502071600832003580000102003920039200392003920039
8002420038155003925800101080000108000050640000012001920038200389996310046800102080000201600002003820038118002110910108000010005020221611892003580000102003920039200392003920039
80024200381550050725800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010005020716001162003580000102003920039200392003920039
80024200381550123925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010105020111600592003580000102003920039200392003920039
8002420038156003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010005020101600992003580000102003920039200392003920039