Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USUBW2 (vector, 4S)

Test 1: uops

Code:

  usubw2 v0.4s, v0.4s, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037163611687251000100010002646800020182037203715723189510001000200020372037111001100000730116111787100020382038203820382038
10042037163611687251000100010002646800020182037203715723189510001000200020372037111001100000730116111787100020382038203820382038
10042037150611687251000100010002646800020182037203715723189510001000200020372037111001100000730116111787100020382038203820382038
10042037160611687251000100010002646800020182037203715723189510001000200020372037111001100003730116111787100020382038203820382038
10042037160611687251000100010002646800020182037203715723189510001000200020372037111001100000730116111787100020382038203820382038
10042037150611687251000100010002646800020182037203715723189510001000200020372037111001100000730116111787100020382038203820382038
10042037160611687251000100010002646800020182037203715723189510001000200020372037111001100000730116111787100020382038203820382038
10042037150611687251000100010002646800020182037203715723189510001000200020372037111001100000730116111787100020382038203820382038
10042037150611687251000100010002646800020182037203715723189510001000200020372037111001100000730116111787100020382038203820382038
10042037150611687251000100010002646800020182037203715723189510001000200020372037111001100000730116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  usubw2 v0.4s, v0.4s, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715506119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
102042003715606119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
102042003715506119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
102042003715506119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
102042003715506119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
102042003715506119687251010010010000100100005002847680020018020037200371842931874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
102042003715506119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
102042003715506119687251010010010000100100005002847680020018020084200371842231874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038
102042003715506119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000710011611200340100001002003820038200382003820038
102042003715508919687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000710011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037155000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102013420132200852008620085
10024201321560012264176102019665431002512100121710304662848963020018200372003718444111880410164221032420203262008520084211002110910101000010300205006852242219785010000102008520038200842008620086
1002420085155111110201031968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010001006402162219785010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000306402161219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162319785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  usubw2 v0.4s, v1.4s, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371550253196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001001007101161119791100001002003820038200382003820038
10204200371550889196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371560876196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007351161119791100001002003820038200382003820038
1020420037155061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371550739196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371550928196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037155061196873910100100100001001000050028476801200182003720037184223187611010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371550595196872510100100100001001000050028476800200182003720037184223187451010020010168200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715508451968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010063007101161119791100001002003820038200382003820038
10204200371550799196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820086200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch call (8e)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371550065924616048971968725100101010024161045665285409502001820037200371844431876710010201000020200002003720037111002110091010100001021958074645632199131010000102003820038200382003820038
1002420037161110021012486195882051009715101201711520602859227020018200372003718444318767100102010169202000020037200371110021100910101000010609064021622197850010000102003820038200382003820038
10024200371550000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110091010100001000064021622197850010000102003820038200382003820038
10024200371550000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110091010100001000064021622197850010000102003820038200382003820038
10024200371550000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110091010100001000064021622197850010000102003820038200382003820038
10024200371560000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110091010100001000064021622197850010000102003820038200382003820038
10024200371550000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110091010100001000064021622197850010000102003820038200382003820038
10024200371550000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110091010100001000064021622197850010000102003820038200382003820038
100242003715500000004411968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110091010100001003264021622197850010000102003820038200382003820038
100242003715500001200611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110091010100001040064021622197850010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  usubw2 v0.4s, v8.4s, v9.8h
  usubw2 v1.4s, v8.4s, v9.8h
  usubw2 v2.4s, v8.4s, v9.8h
  usubw2 v3.4s, v8.4s, v9.8h
  usubw2 v4.4s, v8.4s, v9.8h
  usubw2 v5.4s, v8.4s, v9.8h
  usubw2 v6.4s, v8.4s, v9.8h
  usubw2 v7.4s, v8.4s, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060156000000152258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000000000511031611200350800001002003920039200392003920039
802042003815500000040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000000030511011611200350800001002003920039200392003920039
802042003815600000040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815500000040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815500000040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
8020420038155000000105258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381550000001025258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815500000040258010010080000100800005006400000200193200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815600000040258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000000030511011611200350800001002003920039200392003920039
802042003815500000061258010010080000100800005006400000200190200382003899733999680100200800002001600002003820038118020110099100100800001000020030511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715503925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050201816011132003500080000102003920039200392003920039
8002420038155021625800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050201416011142003500080000102003920039200392003920039
8002420038155011525800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000050201316012132003500080000102003920039200392003920039
800242003815503925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050201216014132003500080000102003920039200392003920039
8002420038155126225800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050201316014122003500080000102003920039200392003920039
80024200381560148258001010800001080000506400000120019200382003899963100188001020800002016000020038200381180021109101080000100024050201416014122003500080000102003920039200392003920039
8002420038161015725800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050201216212142003500080000102003920039200392003920039
8002420038155128325800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000050201316013122003500080000102003920039200392003920039
800242003815606225800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000050201016014142003500080000102003920039200392003920039
800242003815506225800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000050201316014122003500080000102003920039200392003920039