Firestorm: USUBW (vector, 4S) measurements

Code:

  usubw v0.4s, v0.4s, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	0	0	0	71	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	0	73	2	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	3	0	6	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1687	49	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	6	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->2

Code:

  usubw v0.4s, v0.4s, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	155	0	105	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	208	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	168	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	3	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	12	84	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	107	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20085	20085	20086	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3c	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	156	0	0	0	0	0	0	2	0	66	19687	25	10010	10	10000	10	10000	50	2847680	1	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	7913	0	755	14	81	17	14	19967	4	10000	10	20228	20273	20228	20228	20274
10024	20262	157	0	0	0	0	540	352	2	0	2502	19632	122	10071	12	10060	14	10760	71	2854095	1	0	20198	20260	20084	18459	20	18860	10772	22	10829	22	21660	20274	20275	6	1	10021	10	9	10	10	10000	10	0	2	0	0	10090	2	757	14	73	15	12	19948	4	10000	10	20272	20275	20273	20314	20178
10024	20275	157	0	1	4	5	660	440	2	0	66	19687	25	10010	10	10000	10	10000	50	2847680	1	0	20018	20037	20037	18444	7	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	2	2	2	1	3	0	716	5	49	11	12	19859	2	10000	10	20275	20226	20038	20228	20275
10024	20274	157	0	0	5	5	672	440	3	0	2949	19632	117	10071	14	10012	12	10760	71	2853731	1	0	20198	20274	20274	18444	19	18879	10930	24	10000	24	21656	20276	20273	7	1	10021	10	9	10	10	10000	10	0	2	0	0	9935	4	685	21	33	11	11	19785	0	10000	10	20085	20085	20038	20038	20038
10024	20037	161	0	0	0	0	543	0	2	3	6508	19643	62	10075	10	10048	13	10456	72	2851529	1	0	20234	20226	20085	18456	15	18823	10622	22	10506	22	21326	20179	20132	9	1	10021	10	9	10	10	10000	10	0	0	0	0	0	4	800	9	57	17	13	19895	2	10000	10	20274	20275	20180	20182	20369
10024	20271	163	1	0	0	0	0	0	2	0	3141	19610	118	10038	13	10048	11	10608	50	2850246	1	0	20126	20226	20180	18450	18	18842	10622	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	2	0	2	1	7525	2	776	13	33	18	16	20057	0	10000	10	20038	20038	20038	20038	20038
10024	20178	163	1	0	2	0	0	0	1	0	3840	19674	25	10038	12	10000	13	10152	71	2847680	1	0	20090	20180	20320	18448	8	18852	10622	24	10990	20	21312	20418	20084	9	1	10021	10	9	10	10	10000	10	2	0	3	0	13815	0	644	8	16	10	10	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	2	0	154	19687	25	10010	10	10000	10	10000	50	2847680	1	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	644	8	16	8	8	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	0	0	0	0	2	0	66	19687	25	10010	10	10000	10	10000	50	2847680	1	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	644	10	16	10	10	19785	4	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	2	0	327	19687	25	10010	10	10000	10	10000	50	2847680	1	0	20018	20037	20086	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	644	10	16	5	10	19785	0	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->3

Code:

  usubw v0.4s, v1.4s, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	155	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	0	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	0	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	0	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	0	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	0	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	82	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	0	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	0	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	0	0	0	0	101	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	0	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	0	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	0	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	0	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	155	0	0	0	0	0	2	148	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	644	11	16	11	12	19785	0	10000	10	20085	20038	20038	20038	20038
10024	20037	155	0	0	0	12	0	2	62	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	644	11	16	8	8	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	0	0	0	2	62	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	644	11	16	12	11	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	2	110	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	644	11	16	11	11	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	2	125	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	644	11	16	11	11	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	2	66	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	644	11	16	11	12	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	0	0	0	2	66	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	644	11	16	11	12	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	0	0	0	2	66	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	644	9	16	11	6	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	2	66	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	644	6	16	11	12	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	2	731	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	644	9	16	9	10	19785	0	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  usubw v0.4s, v8.4s, v9.4h
  usubw v1.4s, v8.4s, v9.4h
  usubw v2.4s, v8.4s, v9.4h
  usubw v3.4s, v8.4s, v9.4h
  usubw v4.4s, v8.4s, v9.4h
  usubw v5.4s, v8.4s, v9.4h
  usubw v6.4s, v8.4s, v9.4h
  usubw v7.4s, v8.4s, v9.4h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20038	156	0	0	0	0	0	0	82	25	80100	100	80000	100	80000	500	640000	1	20019	0	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	5110	2	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	0	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	156	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	0	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	5110	2	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20019	0	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	5110	1	22	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	1	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20083	0	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	82	25	80100	100	80000	100	80000	500	640000	0	20019	0	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	6	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	0	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	3	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	0	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	298	25	80100	100	80000	100	80000	500	640000	1	20019	0	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	0	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	5110	1	16	1	1	20035	0	80000	100	20039	20039	20039	20039	20039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20059	155	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	2	5	16	4	6	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	3	324	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	0	10	16	4	3	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	1	0	5020	0	0	8	16	4	9	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	156	3	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	0	8	16	4	4	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	1	4	16	7	6	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	0	5	16	7	7	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	156	0	1803	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	1	3	16	4	7	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	81	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	0	10	16	4	3	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	0	8	16	4	4	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	6	609	25	80010	10	80000	10	80000	50	640000	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	5020	0	0	6	16	7	4	20035	80000	10	20039	20039	20039	20039	20039

USUBW (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations