Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

USUBW (vector, 8H)

Test 1: uops

Code:

  usubw v0.8h, v0.8h, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037160061168725100010001000264680201820372037157231895100010002000203720371110011000073316111787100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371599061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037160061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037160061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037160061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037160061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037160061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371512061168725100010001000264680201820372037157231895100010002000203720371110011000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  usubw v0.8h, v0.8h, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155000124196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715504061196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715600061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100107101161119791100001002003820038200382003820038
102042003715600061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002008720038200382003820038
102042003715600061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200842003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715510061196872510115100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100007341161119791100001002003820038200382003820038
102042003715500061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715600061196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715500061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101162119791100001002003820038200382003820038
102042003715500061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037155000000000611968725100101010000101000050284768015200182003720037184443187671001020100002020000200372003711100211091010100001000000064044163619785010000102003820038200382003820038
1002420037155000000000611968725100101010000101000050284768014200182003720037184443187671001020100002020000200372003711100211091010100001000000064043163319785010000102003820038200382003820038
1002420037155000000000611968725100101010000101000050284768014200182003720037184443187671001020100002020000200372003711100211091010100001000000064043163319785010000102003820038200382003820038
1002420037156000000000611968725100101010000101000050284768014200182003720037184443187671001020100002020000200372003711100211091010100001000000064043163319785010000102003820038200382003820038
100242003715500000000019011968725100101010000101000050284768014200182003720037184443187671001020100002020000200372003711100211091010100001000000064043163319785010000102003820038200382003820038
1002420037155000000000611968725100101010000101000050284768014200182003720037184443187671001020100002020000200372003711100211091010100001000000064043163319785010000102003820038200382003820038
1002420037155000000000611968725100101010000101000050284768014200182003720037184443187671001020100002020000200372003711100211091010100001000000064043163319785010000102003820038200382003820038
10024200371550000001200611968725100101010000101000050284768014200182003720037184443187671001020100002020000200372003711100211091010100001000000064043163319785010000102003820038200382003820038
1002420037155000000300611968725100101010000101000050284768014200182003720037184443187671001020100002020000200372003711100211091010100001000010064043163319785010000102003820038200382003820038
1002420037155000000000611968725100101010000101000050284768014200182003720037184443187671001020100002020000200372003711100211091010100001000000064043163319785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  usubw v0.8h, v1.8h, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155000000611968725101001001000010010152500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000002509000071011611197910100001002003820038200382003820038
102042003715500000068196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000600000071011611197910100001002003820038200382003820038
1020420037155000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000001003000071011611197910100001002003820038200382003820038
102042003715500024006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000050186000071011611197910100001002003820038200382003820038
10204200371550000003461968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000000066000071011611197910100001002003820038200382003820038
102042003715600000061196872510100100100001191000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000503000071011611197910100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000503000071011611197910100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000003000071011611197910100001002003820038200382003820038
1020420037155000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000004803000071011611197910100001002003820038200382003820038
1020420037155000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000004021000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715606119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100246402162219785010000102003820038200382003820038
10024200371550611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010096402162219785010000102003820038200382003820038
100242003715606119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100156402162219785010000102003820038200382003820038
100242003715506119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100156402162219785010000102003820038200382003820038
100242003715512611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715506119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100186402162219785010000102003820038200382003820038
10024200371551225119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100216402162219785010000102003820038200382003820038
10024200371550611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010036402162219785010000102003820038200382003820038
10024200371560611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010066402162219785010000102003820038200382003820038
10024200371550611968725100101010000101000050285152912001820037200371844431876710010201000020200002003720037111002110910101000010196402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  usubw v0.8h, v8.8h, v9.8b
  usubw v1.8h, v8.8h, v9.8b
  usubw v2.8h, v8.8h, v9.8b
  usubw v3.8h, v8.8h, v9.8b
  usubw v4.8h, v8.8h, v9.8b
  usubw v5.8h, v8.8h, v9.8b
  usubw v6.8h, v8.8h, v9.8b
  usubw v7.8h, v8.8h, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000313511021611200350800001002003920039200392003920039
802042003815500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000087511011611200350800001002003920039200392003920088
802042003815600402580100100800001218000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000012511011612200950800001002003920039200392003920039
80204200381550040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100043511011611200350800001002003920039200392003920039
80204200381550040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
80204200381550040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100003511011611200350800001002003920039200392003920039
80204200381550061258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100010511011611200350800001002003920039200392003920039
80204200381550040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100010511011611200350800001002003920039200392003920039
80204200381550040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100010511011611200350800001002003920039200392003920039
80204200381550040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100010511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200401550012392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010002050200021603320035080000102003920039200392003920039
80024200381560003522580010108000012800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010001050200021602220035080000102003920039200392003920039
8002420038156000812580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010001050200021602320035080000102003920039200392003920039
8002420038155000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010003050200021602320035080000102003920039200392003920039
8002420038155000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010002650200021604420035080000102003920039200392003920039
8002420038155000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010004050200031602220035080000102003920039200392003920039
80024200381550003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100003350200031602220035080000102003920039200392003920039
800242003815500123925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100001850205021602220035080000102003920039200392003920039
8002420038155000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010007350200021603520035080000102003920039200392003920039
8002420038161000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010004350200021602320035080000102003920039200392003920039