Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

UXTL (4S)

Test 1: uops

Code:

  uxtl v0.4s, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire (01)cycle (02)03081e3f4e51inst issue (52)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst neon or fp (9a)a8acc2cfd5d6ddinst fetch restart (de)e0? fp/simd (ee)f5f6f7f8fd
10042037160061168625100010001000264521020182037203715713189510001000100020372037111001100000073316111854100020382038203820382038
10042037160061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820862038
10042037160061168625100010001000264521020182037203715713189510001000100020372037111001100000273116111786100020382038203820382038
10042037150061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037160061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037160061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371600233168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521020182037203715713189510001000100020372037111001100010073116111786100020382038203820382038
10042037160061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
10042037150061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  uxtl v0.4s, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire (01)cycle (02)0307080a0b18191e1f3a3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc2branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
102042003715500000000014519686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000300071021622197910100001002003820038200382003820038
10204200371550000000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071021622197910100001002003820038200382003820038
10204200371550000000008419686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071021622197910100001002003820038200382003820038
10204200371550000000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071021622197910100001002003820038200382003820038
10204200371560000000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071021622197910100001002003820038200382003820038
102042003715500000000010319686251010010010000100100005002848785020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071021622197910100001002003820038200382003820038
102042003715500000012006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071021622197910100001002003820038200382003820038
10204200371550000000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071021622197910100001002003820038200382003820038
102042003715500000000083119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071021622197910100001002003820038200382003820038
102042003716100000000011019686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire (01)cycle (02)030b1e3f4e51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1002420037156002141968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010006402162319786010000102003820038200382003820038
100242003715500611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010006402162219786010000102003820038200382003820038
100242003715500611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010006402162319786010000102003820038200382003820038
1002420037155001031968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010006402162219786010000102003820038200382003820038
100242003715600611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010006402162219786010000102003820038200382003820038
100242003715600611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010006402162219786010000102003820038200382003820038
10024200371560017241968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010006402162219786010000102003820038200382003820038
1002420037156002511968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010006402162219786010000102003820038200382003820038
100242003715500611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010006402162319786010000102003820038200382003820038
100242003715500611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010006402162319786010000102003820085200382003820038

Test 3: throughput

Count: 8

Code:

  uxtl v0.4s, v8.4h
  uxtl v1.4s, v8.4h
  uxtl v2.4s, v8.4h
  uxtl v3.4s, v8.4h
  uxtl v4.4s, v8.4h
  uxtl v5.4s, v8.4h
  uxtl v6.4s, v8.4h
  uxtl v7.4s, v8.4h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)03080b18191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
802042003815600000005992580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
802042003815600000005192580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381560000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
802042003815500000001412580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381550000000292580172100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381550000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511805900200350800001002003920039200392003920039
80204200381550000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
802042003815500000005992580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381550000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381550000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire (01)cycle (02)030708090b0f18191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc2cfd2icache miss (d3)d5d6d9ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
800242003915500000000008125800101080000108000050640000020135202392024499962210018800102080000208000020038200381180021109101080000100020122048051100047641320229080000102029620290202872023720290
80024202871570101055669352119332580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000250920035901320307080000102023920238202882029120240
800242023915701000456723520671428048010804671080580506415480200572028420292100382610127806002080584208058520288202863180021109101080000102220042325051250027002220229080000102033820293202942029020345
80024202911572001056669440032442580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000200050890018821220154080000102035020338202882033720380
80024203431580000036936616031841598075310805641080585506446161202122038820399100563910202806932080779208068020391203918180021109101080000100002003278050200011601120035080000102003920039200392008920193
80024202881570101035660528016162580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000021178051400028601120035080000102003920039200392003920039
800242003815500000007921760120713880290108056210804865064076802001920038200389996310018800102080000208000020038200381180021109101080000100000002325050200011629420035180000102029220243203432039420451
800242014116201010841056440016631428029010805601080194506462100200192003820038999631001880010208000020800002003820038118002110910108000010200000470050200011601120035080000102003920039200392003920039
80024200381600000000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000000050200011601120035080000102003920039200392003920039
80024200381550000000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000000050200011601120035080000102003920039200392003920039