Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UZP1 (vector, 16B)

Test 1: uops

Code:

  uzp1 v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371600000006116872510001000100026468002018203720371572318951000100020002037203711100110000000000073216221787100020382038203820382038
100420371600000006116872510001000100026468002018203720371572318951000100020002037203711100110000000000073216211787100020382038203820382038
100420371600000006116872510001000100026468002018203720371572318951000100020002037203711100110000000000073116221787100020382038203820382038
1004203715000000010316872510001000100026468002018203720371572318951000100020002037203711100110000000000073216221787100020382038203820382038
100420371600000306116872510001000100026468002018203720371572318951000100020002037203711100110000000100073216221787100020382038203820382038
100420371600000006116872510001000100026468002018203720371572318951000100020002037203711100110000000000073216221787100020382038203820382038
100420371500000006116872510001000100026468002018203720371572318951000100020002037203711100110000000000073216221787100020382038203820382038
100420371500000006116872510001000100026468002018203720371572318951000100020002037203711100110000000000073216211787100020382038203820382038
100420371600000006116872510001000100026468002018203720371572318951000100020002037203711100110000000000073216221787100020382038203820382038
100420371600000006116872510001000100026468002018203720371572318951000100020002037203711100110000000000073216121787100020382038203820382038

Test 2: Latency 1->2

Code:

  uzp1 v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715500000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021611197910100001002003820038200382003820038
10204200371560001204071968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000371011611197910100001002003820038200382003820038
1020420037155000004661968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820227
1020420037155002001721968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000371011610197910100001002003820038200382003820038
102042003715500000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037155000001891968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037155000001461968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037156000904491968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715500000611967625101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037156000007971968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)18191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037155110002681968725100101010000101000050284768010200182003720037184440318767100102010000202000020037200371110021109101010000100006440816881978510000102003820038200382003820038
1002420037155110002681968725100101010000101000050284768010200182003720037184440318767100102010000202000020037200371110021109101010000100006440101611111978510000102003820038200382003820038
10024200371551100021711968725100101010000101000050284768000200182003720037184440318767100102010000202000020037200371110021109101010000100006440121611111978510000102003820038200382003820038
1002420037155110002681968725100101010000101000050284768010200182003720037184440318767100102010000202000020037200371110021109101010000100006440101610101978510000102003820038200382003820038
1002420037155110002681968725100101010000101000050284768000200182003720037184440318767100102010000202000020037200371110021109101010000100006440516881978510000102003820038200382003820038
10024200371561100026819687251001010100001010000502847680002001820037200371844403187671001020100002020000200372003711100211091010100001000064401016861978510000102003820038200382003820038
1002420037155110002185196872510010101000010100005028476801020018200372003718444031876710010201000020200002003720037111002110910101000010000644011161051978510000102003820038200382003820038
100242003715011000268196872510010101000010100005028476803420018200372003718444731876710010201000020200002003720037111002110910101000010000644051610101978510000102003820038200382003820038
100242003715011000268196872510010101000010100005028476800020018200372003718444031876710010201000020200002003720037111002110910101000010000644010161051978510000102003820038200382003820038
1002420037150110002681968725100101010000101000050284768000200182003720037184440318767100102010000202000020037200371110021109101010000100006440101611101978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uzp1 v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371550000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371550003611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371550000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715500012611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371550000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011612197910100001002003820038200382003820038
102042003715600012611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371550000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371550000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715500012611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371550000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037155000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000064021622197850010000102003820038200382003820038
1002420037155000000891968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000064021622197850010000102003820038200382003820038
1002420037156000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000064021622197850010000102003820038200382003820038
1002420037155000000611966725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000064022422197850010000102003820038200382003820038
10024200371550000120611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000064021622197850010000102003820038200382003820038
1002420037155000000821968725100101010000101000050284768020018200372003718444318767100102010000202000020037200835110021109101010000100031009993072734943199302010000102022720276202752027620275
1002420274157115579244030501964311610086121006014107607128540952019820275202731846124188711077120108222021684202742027361100211091010100001000000210053274335724199685010000102003820038200852003820038
1002420037156000000611968725100101010000101000055284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000064021622197850010000102008620038202272022820228
10024200371550000008219687251001010100001010000502847680200182003720037184442618858107712010823202033820272202746110021109101010000102200140064043342199440010000102003820038200382003820038
100242003715600000061196321331002417100721210760602855378202342032220321184572718786100102010000222198020274203197110021109101010000102000000064021622197850010000102037220369203682013420371

Test 4: throughput

Count: 8

Code:

  uzp1 v0.16b, v8.16b, v9.16b
  uzp1 v1.16b, v8.16b, v9.16b
  uzp1 v2.16b, v8.16b, v9.16b
  uzp1 v3.16b, v8.16b, v9.16b
  uzp1 v4.16b, v8.16b, v9.16b
  uzp1 v5.16b, v8.16b, v9.16b
  uzp1 v6.16b, v8.16b, v9.16b
  uzp1 v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004815500021004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511021611200350800001002003920039200392003920039
8020420038155000189004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381550001200040126801001178000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381550000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381550000008225801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381550000006825801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381560000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
802042003815500084004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000030511011611200350800001002003920039200392003920039
80204200381550000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039
80204200381550000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039155006025800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020171612720035080000102003920039200392003920039
8002420038155133392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502010169620035080000102003920039200392003920039
8002420038155057392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502091671020035080000102003920039200392003920039
80024200381560441392580010108000010801205064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502010167920035080000102003920039200392003920039
8002420038155063925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020101610820035080000102003920039200392003920039
800242003815505439258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050208165820035080000102003920039200392003920039
800242003815601688125800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100135020101610620035080000102003920039200392003920039
800242003815602073925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020101610720035080000102003920039200392003920039
8002420038155027639258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050209166820035080000102003920039200392003920039
80024200381550039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050209169820035080000102003920039200392003920039