Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UZP1 (vector, 2D)

Test 1: uops

Code:

  uzp1 v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150306116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160906116872510001000100026468002018203720371572318951000100020002037203711100110000373116111787100020382038203820382038
10042037160006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371501206116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160906116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371602706116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371602708316872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037170006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  uzp1 v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155000027006119687251010010010000100100005002847680020018200372003718429718741101002001000820020016200372003711102011009910010010000100000000111718001600198010100001002003820038200382003820038
102042003715500000006119687251010010010000100100005002847680020018200372003718429618741101002001000820020016200372003711102011009910010010000100000030111717001600198010100001002003820038200382003820038
102042003715500000006119687251010010010000100100005002847680020018200842008618429718741101002001000820020016200372003711102011009910010010000100000000111717001600198020100001002003820038200382003820038
102042003715500000006119687251010010010000100100005002847680020018200372003718429618741101002001000820020016200372003711102011009910010010000100000000111717001600198010100001002003820038200382003820038
102042003715500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000030000710011611197910100001002003820038200382003820038
102042003715500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000000710011611197910100001002003820038200382003820038
102042003715500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000000710011611197910100001002003820038200382003820038
1020420037155000000044119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000000710011611197910100001002003820038200382003820038
102042003715500000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000000710011611197910100001002003820038200382003820038
102042003715500000006619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000000710011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000010931967625100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820084200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038
1002420037149000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010001640316331978510000102003820038200382003820038
1002420037150100611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640316331978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uzp1 v0.2d, v1.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500017019687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500018919687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820235200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100320071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382013320038
1020420037150016119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500012619687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500010519687251010010010000100100005002847680120018200372003718422318745101002041000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037149006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715500126119687251001212100001210000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010018064041643197872010000102003820038200382003820038
100242003715500031319687251001012100001010000502847680120018020037200371844431876710012201000020200002003720037111002110910101000010516064481684197872010000102003820038200382003820038
100242003715500010319687251001210100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010339064021688197870010000102003820038200382003820038
1002420228155000611968725100121010000101000050284768012001802008520037184443187671001220100002020000200372003711100211091010100001020064021622197850010000102003820038200382003820038
1002420037156000611968725100121010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000064021622197850010000102003820038200382003820038
10024200371550006119687251001210100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010418064441644197872010000102003820038200382003820038
1002420037156000425196872510012101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100126064021622197850010000102003820038200382003820038
100242003715500061196872510012101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000104117064021622198530010000102003820038200382003820038
1002420037155000611968725100101010000101000050284768012001802003720037184483187671001020100002020000200372003711100211091010100001033064021622197850010000102003820038200382003820038
1002420037155000611968725100101210000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001089064021622197850010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uzp1 v0.2d, v8.2d, v9.2d
  uzp1 v1.2d, v8.2d, v9.2d
  uzp1 v2.2d, v8.2d, v9.2d
  uzp1 v3.2d, v8.2d, v9.2d
  uzp1 v4.2d, v8.2d, v9.2d
  uzp1 v5.2d, v8.2d, v9.2d
  uzp1 v6.2d, v8.2d, v9.2d
  uzp1 v7.2d, v8.2d, v9.2d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059155004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000511004162220035800001002003920039200392003920039
8020420038155004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000511002162220035800001002003920039200392003920039
8020420038156004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000511002162220035800001002003920039200392003920039
8020420038155004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000511002162220035800001002003920039200392003920039
8020420038156004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000511002163220035800001002003920039200392003920039
80204200381550023025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000511003162220035800001002003920039200392003920039
8020420038155004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000511002162220035800001002003920039200392003920039
8020420038155008225801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000511002162220035800001002003920039200392003920039
8020420038156004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000511002162220035800001002003920039200392003920039
8020420038155004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000511003162220035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039156000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000005020716972003500080000102003920039200392003920039
8002420038155000067258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000005022716442003500080000102003920039200392003920039
8002420038155000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000005020416442003500080000102003920039200392003920039
8002420038167000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000005020716432003500080000102003920039200392003920039
800242003815500254039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000005020416442003500080000102003920039200392003920039
8002420038156000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000005020716482003500080000102003920039200392003920039
80024200381560120039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000005020416442003500080000102003920039200392003920039
800242003815500005852580010108000010800005064000020019201002010310005810018800102080099201600002017120038118002110910108000010200025020735862011300080000102013920091201042009020039
8002420038155000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000005020416442003500080000102003920039200392003920039
8002420038155000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010000005020716342003500080000102003920039200392003920039