Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UZP1 (vector, 4H)

Test 1: uops

Code:

  uzp1 v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073316221829100020382038203820382038
1004203716126116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073224221787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203716010316872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  uzp1 v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037155061196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037156061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382007620038
1020420037161061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371550251196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100400007101161119791100001002003820038200382003820038
1020420037155061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037155061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037155061196872510100100100001001000054628476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037155061196872510100100100001001000050028476800200182003720037184220318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037155061196872510100100100001001000050028476801200182003720037184220318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640316221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000031640216321978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100002490640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715021321887196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000536196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uzp1 v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371550611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371560611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100057071011611197910100001002003820038200382003820038
10204200371550611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010010071011611197910100001002003820038200382003820038
102042003715606119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100069071011611197910100001002003820038200382003820038
1020420037155397261968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371550611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371560611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371550611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371560611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037155000000871968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000064021622197850010000102003820038200382003820038
10024200371550000001561968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000064021622197850010000102003820038200382003820038
100242003715500000045121968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000064021622197850010000102003820038200382003820038
1002420037156000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000164021622197850010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000030064021622197850010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000100064021622197850010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000064021622197850010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000064021622197850010000102003820038200382003820038
1002420037156000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000064021622197850010000102003820038200382003820038
1002420037155000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000064021622197850010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uzp1 v0.4h, v8.4h, v9.4h
  uzp1 v1.4h, v8.4h, v9.4h
  uzp1 v2.4h, v8.4h, v9.4h
  uzp1 v3.4h, v8.4h, v9.4h
  uzp1 v4.4h, v8.4h, v9.4h
  uzp1 v5.4h, v8.4h, v9.4h
  uzp1 v6.4h, v8.4h, v9.4h
  uzp1 v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200381560004025801001008000010080000500064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100013511041644200350800001002003920039200392003920039
802042003815600061025801001008000010080000500064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100003511041654200350800001002003920039200392003920039
802042003815500010725801001008000010080000500064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100093511041635200350800001002003920039200392003920039
802042003815500039258010010080000100800005000641648020019200382003899733999680100200800002001600002003820038118020110099100100800001000087511051612200350800001002003920039200392003920039
80204200381550002925801081008000810080020500064013202001920038200389973399968010020080000200160000200382003811802011009910010080000100013511051645200350800001002003920039200392003920039
80204200381550004025801001008000010080000500064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100010511051645200350800001002003920039200392003920039
80204200381550004025801001008000010080000500064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100010511041645200350800001002003920039200392003920039
80204200381560004025801251008000010080000500064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100016511031635200350800001002003920039200392003920039
80204200381551004025801001008009510080000500064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100006511251655200350800001002003920039200392003920039
80204200381551004025801251258000010080000500064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100020511041655200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715503925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000102305020512163520035080000102003920039200392003920039
800242003815512392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010440502004164320035080000102003920039200392003920039
800242003815503925800101080000108000050640000120019200382003899963100188001020800002016000020135200381180021109101080000105712502003163320035080000102003920039200392003920039
8002420038155039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001020502004164420035080000102003920039200392003920039
8002420038155039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001060502005165520035080000102003920039200392003920039
8002420038155039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001040502005164220035080000102003920039200392003920039
80024200381560609258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001050502005163520035080000102003920039200392003920039
8002420038156039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001049502004165320035080000102003920039200392003920039
80024200381550392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010024502005163320035080000102003920039200392003920039
80024200381550392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010240502004164320035080000102003920039200392003920039