Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UZP2 (vector, 2D)

Test 1: uops

Code:

  uzp2 v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371600061168725100010001000264680120182037203715723189510001000200020372037111001100010073116111787100020382038203820382038
100420371500061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203716001261168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371600082168725100010001000264680120182037203715723189510001000200020372037111001100000073117111787100020382038203820382038
1004203716000128168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371600061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371600061168725100010001000264680120182037203715723189510001000200020372037111001100010073116111787100020382038203820382038
100420371600061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371600061168725100010001000264680120182037203715723189510001000200020372037111001100000073116121787100020382038203820382038
100420371600061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  uzp2 v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155120611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
102042003715500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
102042003715500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000371021622197910100001002003820038200382003820038
102042003715500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
102042003715500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
102042003715500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010001071021622197910100001002003820038200382003820038
102042003715500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010001071021622197910100001002003820038200382003820038
102042003715500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
102042003715500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
102042003715500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010004071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371610011151968725100101010000101000050284768000200182003720037184333187671001020100002020000200372003711100211091010100001000006400216221978510000102003820038200382003820038
100242003716100611968725100101010000101000050284768000200182003720037184443187671001020100002020000200372003711100211091010100001000006400216221978510000102003820038200382003820038
100242003715500611968725100101010000101000050284768000200182003720037184443187671001020100002020000200372003711100211091010100001000006400216221978510000102003820038200382003820038
100242003715600611968725100101010000101000050284768000200182003720037184443187671001020100002020000200372003711100211091010100001000006400216221978510000102003820038200382003820038
100242003715500611968725100101010000101000050284768000200182003720037184443187671001020100002020000200372003711100211091010100001000006400216221978510000102003820038200382003820038
100242003715500611968725100101010000101000050284768000200182003720037184443187671001020100002020000200372003711100211091010100001000006400216221978510000102003820038200382003820038
100242003715500611968725100101010000101000050284768000200182003720037184443187671001020100002020000200372003711100211091010100001000006400216221978510000102003820038200382003820038
100242003715500611968725100101010000101000050284768000200182003720037184443187671001020100002020000200372003711100211091010100001000006400216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768000200182003720037184443187671001020100002020000200372003711100211091010100001000006400216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768000200182003720037184443187671001020100002020000200372003711100211091010100001000006400216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uzp2 v0.2d, v1.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715600000150611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100992002110010010000100000071041611197910100001002003820038200382003820038
1020420037156000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099010010010000100000071011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476800200222003720037184223187451010020010000200200002003720037111020110099010010010000100000071011611197910100001002003820038200382003820038
10204200371550000024061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099010010010000100000071011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099010010010000100000071011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099010010010000100000071011611197910100001002003820038200382003820038
10204200371550000090631196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099010010010000100000071011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099010010010000100000071011611197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099010010010000100000071011611197910100001002003820038200382003820038
102042003715600000159061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099010010010000100003071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715500000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006403162219785010000102003820038200382003820038
100242003715500000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715500000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402242219785010000102003820038200382003820038
100242003715500000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000002006404162219785010000102003820038200382003820038
100242003715500000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000010306402162219785010000102003820038200382003820038
100242003715500000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000306402162219785010000102003820038200382003820038
100242003715600000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715500000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037155000000000636196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000206126402162219785010000102003820038200382003820038
10024200371550000000120548196872510010101002410100007128476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uzp2 v0.2d, v8.2d, v9.2d
  uzp2 v1.2d, v8.2d, v9.2d
  uzp2 v2.2d, v8.2d, v9.2d
  uzp2 v3.2d, v8.2d, v9.2d
  uzp2 v4.2d, v8.2d, v9.2d
  uzp2 v5.2d, v8.2d, v9.2d
  uzp2 v6.2d, v8.2d, v9.2d
  uzp2 v7.2d, v8.2d, v9.2d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000051102161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000030000051101161120035800001002003920039200392003920039
8020420038150140258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000051101161120035800001002003920039200392003920039
802042003815007052580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000270300051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192008820038997339996801002008000020016000020038200381180201100991001008000010000000000051101161120035800001002003920039200392003920039
80204200381500334258010010080000100800005006400000200192008720038997339996801002008000020016000020038200381180201100991001008000010000000000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815590805258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100005020916222003580000102003920039200392003920039
80024200381550039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100005020216622003580000102003920039200392003920039
80024200381550039258001010800001080000506400000120019200382003899963100188001020800002016000020038200381180021109101080000100005020316222003580000102003920039200392003920039
80024200381550039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000101005020216222003580000102003920039200392003920039
80024200381550039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100025020216362003580000102003920039200392003920039
80024200381556039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100005020316362003580000102003920039200392003920039
80024200381560093258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100005020316322003580000102003920039200392003920039
80024200381550039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100005020216222003580000102003920039200392003920039
80024200381550039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100305020616222003580000102003920039200392003920039
80024200381550039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100005020616362003580000102003920039200392003920039