Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UZP2 (vector, 2S)

Test 1: uops

Code:

  uzp2 v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037160008216872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037160006116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371600010316872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037160006116872510001000100026468020182037203715723189510001000200020372037111001100001073116111787100020382038203820382038
100420371600018416872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037160006116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371600059416872510001000100026596320182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037150006116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037150006116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037160006116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  uzp2 v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371552106119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371611506119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100137101161119791100001002003820038200382003820038
1020420037155006119687251010010010000100100005002847680120018200832008618422318745101002001000020020000200372003711102011009910010010000100107101161119791100001002003820038200382003820038
10204200371561506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371553006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037155006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100037101161119791100001002003820038200382003820038
10204200371552706119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371553006119687251010010010000100100005002847680120018200372003718422318762101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371553906119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100107101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150061196872510010101000010100005028476801200180200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200180200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200180200372003718444031876710010201000020200002003720084211002110910101000010000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200183200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200180200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200180200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037149061196872510010101000010100005028476801200180200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200180200372003718444031876710010201000020200002003720037111002110910101000010200640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200180200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200180200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uzp2 v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0f18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715500000100061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000071011611197910100001002003820038200382003820038
10204200371550000001500103196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000030071011611197910100001002003820038200382003820038
1020420037155000000000117196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000030071011611197910100001002003820038200382003820038
102042003715500000030061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000071011611197910100001002003820038200382003820038
10204200371550000003300611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100000038000071011611197910100001002003820038200382003820038
102042003715500000230061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000071011611197910100001002003820038200382003820038
1020420037155000000120061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000071011611197910100001002003820038200382003820038
102042003715500000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000071011611197910100001002003820038200382003820038
102042003715500000000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000071011611197910100001002003820038200382003820038
1020420037156000000150061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)030918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715500036061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000300640516221978510000102003820038200382003820038
10024200371550000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216231978510000102003820038200382003820038
100242003715500051061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371550000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371550000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715500000131196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371550000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371550000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715500015061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
1002420037155000537061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uzp2 v0.2s, v8.2s, v9.2s
  uzp2 v1.2s, v8.2s, v9.2s
  uzp2 v2.2s, v8.2s, v9.2s
  uzp2 v3.2s, v8.2s, v9.2s
  uzp2 v4.2s, v8.2s, v9.2s
  uzp2 v5.2s, v8.2s, v9.2s
  uzp2 v6.2s, v8.2s, v9.2s
  uzp2 v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815600000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100010511021611200350800001002003920039200392003920039
802042003815500000082258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392013720039
802042008815500000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
802042003815500000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
802042003815500000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
802042003815500000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100030511011611200350800001002003920039200392003920039
802042003815600000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100043511011611200350800001002003920241200392009220039
802042003816100000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100010511011611200350800001002003920039200392003920039
802042003815600000082258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
802042003815500000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715503925800101080000108000050640000002001902003820038999631001880010208000020160000200382003811800211091010800001080502000416112003580000102003920039200392003920039
800242003815503925800101080000108000050640000002001902003820038999631001880010208000020160000200382003811800211091010800001000502000116112003580000102003920039200392003920039
800242003815503925800101080000108000050640000002001902003820038999631001880010208000020160000200382003811800211091010800001000502000316112003580000102003920039200392003920039
8002420038155039258001010800001080000506400000020019020038200389996310018800102080000201600002003820038118002110910108000010609502050116112003580000102003920039200392003920039
8002420038155060925800101080000108000050640000002001902003820038999631001880010208000020160000200382003811800211091010800001009502000216442003580000102003920039200392003920039
800242003815503925800101080000108000050640000002001902003820038999631001880010208000020160000200382003811800211091010800001040502000216112003580000102003920039200392003920039
8002420038155039258001010800001080000506400000020019020038200389996310018800102080000201600002003820038118002110910108000010110502000416112003580000102003920039200392003920039
800242003815603925800101080000108000050640000002001902003820038999631001880010208000020160000200382003811800211091010800001000502000116112003580000102003920039200392003920039
800242003815568125800101080000108000050640000002001902003820038999631001880010208000020160000200382003811800211091010800001010502000316332003580000102003920039200392003920039
800242003815503925800101080000108000050640000002001902003820038999631001880010208000020160000200382003811800211091010800001000502000116112003580000102003920039200392003920039