Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UZP2 (vector, 4S)

Test 1: uops

Code:

  uzp2 v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000373116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715126116872510001000100026468002018203720371572318951000100020002037203711100110000373116111787100020382038203820382038
1004203715014916872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371607416872510001000100026468002018203720371572318951000100020002037203711100110000373116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  uzp2 v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371560097719687251010010010000100100005002847680120018200372003718429618741101002001000820020016200372003711102011009910010010000100001117180160019802100001002003820038200382003820038
1020420037155006119687251010010010000100100005002847680020018200372003718429618740101002001000820020016200372003711102011009910010010000100001117170160019802100001002003820038200382003820038
10204200371610010319687251010010010000100100005002847680020018200372003718429718740101002001000820020016200372003711102011009910010010000100001117170160019802100001002003820038200382003820038
1020420037155006119687251010010010000100100005002847680020018200372003718429718741101002001000820020016200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371550078719687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100030007101161119791100001002003820038200382003820038
10204200371550010319687251010010010000100100005002847680020018200372003718422318763102762001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715500103019687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037156008219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371550082719687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715600105419687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161120034100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003714900061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316421978510000102003820038200382003820038
1002420037150000124196872510010101000010100005028476802200182003720037184443187671001020100002020000200372003711100211091010100001000640416431978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640416341978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316431978510000102003820038200382003820038
100242003715001061196872510010101001211100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640416441978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316441978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182008420037184443187671001020100002020000200372003711100211091010100001000640416341978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316341978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640416341978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640416341978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  uzp2 v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371560000821968725101001001000010010000500284768012001820037200371842971874010100200100082002001620037200371110201100991001001000010001117170160019801100001002003820038200382003820038
10204200371550000611968725101001001000010010000500284768012001820037200371842961874110100200100082002001620037200371110201100991001001000010001117180160019801100001002003820038200382003820038
10204200371550000611968725101001001000010010000500284768012001820037200371843371874010100200100082002001620037200371110201100991001001000010001117180160019802100001002003820038200382003820038
10204200371610000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371550000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037155000018251968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010030007101161119791100001002003820038200382003820038
10204200371550090611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715500008431968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371560000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371550000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371552961968725100101010000101000050284768012001820037200371844431876710010201000020203442003720037111002110910101000010000640316221978510000102003820038200382003820038
1002420037156611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010100640216221978510000102003820038200382003820038
10024200371552291968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371551521968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371551241968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371551451968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037155611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371552101968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000670216221978510000102003820038200382003820038
1002420037155611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715611361968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  uzp2 v0.4s, v8.4s, v9.4s
  uzp2 v1.4s, v8.4s, v9.4s
  uzp2 v2.4s, v8.4s, v9.4s
  uzp2 v3.4s, v8.4s, v9.4s
  uzp2 v4.4s, v8.4s, v9.4s
  uzp2 v5.4s, v8.4s, v9.4s
  uzp2 v6.4s, v8.4s, v9.4s
  uzp2 v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420049156000000002179258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511451677200350800001002003920039200392003920039
802042003815500000090245258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511491699200350800001002003920039200392003920039
802042003815500000000245258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511491694200350800001002003920039200392003920039
802042003815500000000245258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511491699200350800001002003920039200392003920039
802042003815500000000245258010010080000100800945116407681200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511471699200350800001002003920039200392003920039
802042003815600000000245258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511491699200350800001002003920039200392003920039
8020420038156000000002452580100100800001008000050064000002001920038200389973310023801002008000020016000020038200381180201100991001008000010000000000511491699200350800001002003920039200392003920039
802042003816100000000245258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511491699200350800001002003920039200392003920039
8020420038155000000002452580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000005114916914200350800001002003920039200392003920039
802042003815500000000245258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000000511491699200350800001002003920089200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd0d2d5map dispatch bubble (d6)dadbddfetch restart (de)e0? int output thing (e9)ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915510120392580010108000010800005064000010200192003820038999631001880010208000020160000200382003811800211091010800001000005020001160021200350080000102003920039200392003920039
80024200381560000392580010108000010800005064000010200192003820038999631001880010208000020160000200382003811800211091010800001000005020001161017200350080000102003920039200392003920039
800242003815600004192580010108000010800005064000010200192003820038999631001880010208000020160000200382003811800211091010800001000005024001160013200352080000102003920039200392003920039
80024200381550000392580010108000010800005064000010200192003820038999631001880012208000020160000200382003811800211091010800001000005022001160013200350080000102003920039200392003920039
80024200381550000392580012128000010800005064000010200192003820038999631001880010208000020160000200382003811800211091010800001000005020003160011200350080000102003920039200392003920039
80024200381550000392580010108000010800005064000010200192003820038999631001880010208000020160000200382003811800211091010800001000005020001160011200350080000102003920039200392003920039
800242003815500120602580010108000010800005064000000200192003820038999631001880012208000020160000200382003811800211091010800001000005020006160011200350080000102003920039200392003920039
80024200381550000392580010108000012800005064000010200192003820038999631001880012208000020160000200382003811800211091010800001000005020001160011200350080000102003920039200392003920039
800242003815500005562580012128000012800006064000000200192003820038999631001880012208000020160000200382003811800211091010800001000005020001160011200350080000102003920039200392003920039
80024200381550000392580010108000010800005064000010200192003820038999631001880010208000020160000200382003811800211091010800001000005020001160011200350080000102003920039200392003920039