Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

XAR

Test 1: uops

Code:

  xar v0.2d, v0.2d, v1.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100015073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318791000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073216211787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110003073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000373116111787100020382038203820382038
100420371607516872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  xar v0.2d, v0.2d, v1.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371550000000191196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021622197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476802001832003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021622197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021622197910100001002003820038200382003820038
1020420037155000000084196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021642197910100001002003820038200382003820038
102042003715600000001521968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200372110201100991001001000010000214823071021622197910100001002003820038200382003820038
10204200371550100000103196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021632197910100001002003820038200382003820038
102042003715500001200103196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000000103071021622197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000000100071021622197910100001002003820038200382003820038
10204200371550000600107196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021622197910100001002003820038200382003820038
1020420037155000000061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)dfe0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196872510010101000010100005028476800020018200372003718444031876710010201000020200002003720037111002110910101000010000000640051622019785010000102003820038200382003820038
10024200371500061196872510010101000010100005028476800020018200372003718444031876710010201000020200002003720037111002110910101000010000000640021622019785010000102003820038200382003820038
10024200371500061196872510010101000010100005028476801020018200372003718444031876710010201000020200002003720037111002110910101000010000000640021622019785010000102003820038200382003820038
10024200371500061196872510010101000010100005028476801020018200372003718444031876710010201000020200002003720037111002110910101000010022030640021622019785010000102003820038200382003820038
10024200371500061196872510010101000010100005028476801020018200372003718444031876710010201000020200002003720037111002110910101000010000000640021622019785010000102003820038200382003820038
10024200371500061196872510010101000010101525028476800020018200372003718444031876710010201000020200002003720037111002110910101000010000000640021622019785010000102003820038200382003820038
10024200371500061196872510010101000010100005028476801020018200372003718444031876710010201000020200002003720037111002110910101000010000000640021622019785010000102003820038200382003820038
100242003715000726196872510010101000010100005028476801020018200372003718444031876710010201000020200002003720037111002110910101000010000000640021622019785010000102003820038200382003820038
10024200371500061196872510010101000010100005028476801020018200372003718444031876710010201000020200002003720037111002110910101000010400000640021622019785010000102003820038200382003820038
10024200371500061196872510010101000010100005028476800020018200372003718444031876710010201000020200002003720037111002110910101000010000000640021622019785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  xar v0.2d, v1.2d, v0.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371560006119687251010010010000100100005002847680020018200372003718429718741101002001000820020016200372003711102011009910010010000100001117180160019801100001002003820038200382003820038
10204200371560006119687251010010010000100100005002847680020018200372003718429718740101002001000820020016200372003711102011009910010010000100001117170160019802100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371560006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371560006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371550008919687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680120018200372003718422318745101002001082820020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
102042003715601206119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100030007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd2d5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371560103196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100068203160221978510000102003820038200382003820038
1002420037155061196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100064002160221978510000102003820038200382003820038
1002420037155061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100064002160221978510000102003820038200382003820038
1002420037156084196872510010101000010100005028476801200180200712003718444318767100102010000202000020037200371110021109101010000100064002160221978510000102003820038200382003820038
1002420037155061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100064002160221978510000102003820038200382003820038
1002420037155061196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100064002160221978510000102003820038200382003820038
1002420037155061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100064002160221978510000102003820038200382003820038
10024200371550103196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100064002160221978510000102003820038200382003820038
10024200371550726196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000101064002160221978510000102003820038200852003820038
100242003715501171196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100364002160221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  xar v0.2d, v8.2d, v9.2d, #3
  xar v1.2d, v8.2d, v9.2d, #3
  xar v2.2d, v8.2d, v9.2d, #3
  xar v3.2d, v8.2d, v9.2d, #3
  xar v4.2d, v8.2d, v9.2d, #3
  xar v5.2d, v8.2d, v9.2d, #3
  xar v6.2d, v8.2d, v9.2d, #3
  xar v7.2d, v8.2d, v9.2d, #3
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815608225801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051102161120035800001002003920039200392003920039
802042003815604025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101162220035800001002003920039200392003920039
802042003815504025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038155124025801001008000010080000500640000020019200382003899733999680100200803942001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815504025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815504025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815504025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003816504025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038156070525801001008000010080000500640000020019200382003899733999680100200800002001600002003820091118020110099100100800001000351101161120035800001002003920039200392003920039
802042003815504025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915508325800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100035020260616112003500080000102003920039200392003920039
8002420038155123925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020230216112003502080000102003920039200392003920039
800242003816603925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020260116112003500080000102003920039200392003920039
800242003815503925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020260116112003500080000102003920039200392003920039
8002420038155573925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020260116112003500080000102003920039200392003920039
800242003815503925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100105020230116112003500080000102003920039200392003920039
800242003815503925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020230116112003500080000102003920039200392003920039
800242003815608125800101080000108000050640000020019200382003899963100188001020800002016000020139200381180021109101080000100005020264216112003500080000102003920039200392003920039
800242003815563925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020260116112003500080000102003920039200392003920039
800242003815503925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020290216112003500080000102003920039200392003920039