Firestorm: XTN2 (2D) measurements

Code:

  xtn2 v0.4s, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	84	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	3	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	82	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  xtn2 v0.4s, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	155	0	9	657	19687	25	10164	119	10024	113	10304	654	2851529	0	20018	20085	20085	18422	3	18745	10100	200	10000	200	20000	20132	20085	1	1	10201	100	99	100	100	10000	100	3	0	630	710	1	16	1	1	19791	0	10000	100	20038	20038	20086	20038	20038
10204	20037	155	1	318	103	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	51	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	9	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	161	0	24	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20131	18422	3	18763	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	3	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	3	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	103	19687	25	10100	100	10000	100	10152	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	24	346	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	155	0	0	0	0	0	393	0	316	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	363	0	89	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	315	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	336	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	342	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18840	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	306	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	93	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	726	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	0	0	0	192	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	22	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  xtn2 v0.4s, v0.2d

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	50	78	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	3	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10456	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	607	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	26	129	1	1	1	717	0	16	0	0	19800	10000	100	20038	20086	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	12	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	63	3	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	3	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10048	100	10000	500	2847521	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	6	1	1	1	718	0	24	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	9	264	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	3	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	155	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	640	4	16	4	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	640	4	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	4	4	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	3	4	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	3	4	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	2	0	0	0	640	4	16	4	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	4	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	0	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	2	3	19786	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  xtn2 v0.4s, v8.2d
  movi v1.16b, 0
  xtn2 v1.4s, v8.2d
  movi v2.16b, 0
  xtn2 v2.4s, v8.2d
  movi v3.16b, 0
  xtn2 v3.4s, v8.2d
  movi v4.16b, 0
  xtn2 v4.4s, v8.2d
  movi v5.16b, 0
  xtn2 v5.4s, v8.2d
  movi v6.16b, 0
  xtn2 v6.4s, v8.2d
  movi v7.16b, 0
  xtn2 v7.4s, v8.2d

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5e	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	155	0	0	0	0	0	694	25	80116	100	80016	100	80028	500	640196	0	0	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	0	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	0	17	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	29	25	80192	100	80016	100	80028	500	640196	0	0	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	0	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	0	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	12	71	25	80116	100	80016	100	80028	500	640196	0	0	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	0	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	72	25	80116	100	80016	100	80028	500	640196	0	0	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	12	29	25	80116	100	80016	100	80028	500	640196	0	0	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	0	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20065	156	0	0	44	25	80010	10	80000	10	80000	50	640000	1	0	0	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	10030	8	1	1	4	20	2	1	1	7	6	20042	0	30	160000	10	20054	20046	20046	20046	20046
160024	20045	155	0	0	44	25	80010	10	80000	10	80000	50	640000	1	0	0	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	10030	8	1	1	6	20	2	1	1	4	3	20042	0	30	160000	10	20050	20046	20046	20046	20046
160024	20045	155	0	0	44	25	80010	10	80000	10	80000	50	640000	1	0	0	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	37	6	10030	3	1	1	4	20	2	1	1	4	3	20042	0	15	160000	10	20046	20046	20046	20046	20046
160024	20045	155	0	0	44	25	80010	10	80000	10	80000	50	640000	1	0	5	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	1	0	10031	3	3	1	7	23	2	1	1	4	6	20042	3	15	160000	10	20050	20046	20046	20046	20046
160024	20045	155	0	0	1035	25	80010	10	80000	10	80000	50	640000	1	1	5	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	2	0	10026	3	1	1	6	20	2	1	1	7	4	20042	0	15	160000	10	20046	20046	20046	20046	20046
160024	20049	161	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	5	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20046	1	1	160021	10	9	10	10	160000	10	41	0	10029	3	2	1	4	20	2	1	1	3	4	20042	0	15	160000	10	20046	20046	20046	20046	20046
160024	20045	155	0	0	44	25	80010	10	80000	10	80000	50	640000	1	0	0	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	10031	3	1	1	4	20	2	1	1	4	3	20042	0	16	160000	10	20050	20046	20046	20046	20046
160024	20045	155	0	0	987	25	80010	10	80000	10	80000	50	640000	1	1	0	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	10026	3	1	1	3	20	2	1	1	3	4	20042	0	15	160000	10	20046	20046	20046	20046	20046
160024	20045	156	0	0	44	25	80010	10	80000	10	80000	50	640000	1	0	0	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	10028	3	1	1	4	20	4	1	1	4	4	20042	0	15	160000	10	20050	20046	20046	20046	20046
160024	20045	155	0	0	44	25	80010	10	80000	10	80000	50	640000	1	0	0	20026	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	5	0	10027	3	1	1	4	20	2	1	1	8	4	20042	0	15	160000	10	20046	20046	20046	20046	20046

Test 5: throughput

Count: 16

Code:

  xtn2 v0.4s, v16.2d
  xtn2 v1.4s, v16.2d
  xtn2 v2.4s, v16.2d
  xtn2 v3.4s, v16.2d
  xtn2 v4.4s, v16.2d
  xtn2 v5.4s, v16.2d
  xtn2 v6.4s, v16.2d
  xtn2 v7.4s, v16.2d
  xtn2 v8.4s, v16.2d
  xtn2 v9.4s, v16.2d
  xtn2 v10.4s, v16.2d
  xtn2 v11.4s, v16.2d
  xtn2 v12.4s, v16.2d
  xtn2 v13.4s, v16.2d
  xtn2 v14.4s, v16.2d
  xtn2 v15.4s, v16.2d

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2504

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40074	310	0	0	0	0	0	0	1	0	56	0	25	160108	100	160008	100	160023	500	1320129	1	40076	0	40038	40095	20012	0	6	20180	160120	200	160032	200	320064	40038	40100	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	3	0	1	1	1	10118	1	16	1	1	40179	0	160000	100	40039	40344	40039	40058	40157
160204	40095	310	0	0	0	0	0	0	0	0	160	0	25	160108	100	160008	100	160023	500	1280132	0	40066	0	40085	40074	19998	0	6	20036	160123	200	160032	200	320064	40099	40099	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	0	16	1	0	40133	0	160000	100	40039	40096	40142	40086	40039
160204	40038	310	0	0	0	0	0	0	0	0	29	3	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40095	19977	0	6	20063	160120	200	160032	200	320064	40038	40095	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40082	0	160000	100	40058	40157	40157	40058	40096
160204	40095	310	0	0	0	0	0	0	78	0	466	0	25	160123	100	160008	100	160020	500	1280132	0	40076	0	40038	40095	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	0	16	1	0	40035	0	160000	100	40039	40086	40039	40086	40039
160204	40055	310	0	0	0	0	0	0	58	0	30	111	25	160178	100	160008	100	160020	500	5598302	1	40076	0	40095	40095	19978	0	6	20107	160121	200	160032	200	320064	40095	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40096	40039	40096	40096	40096
160204	40095	310	0	0	0	0	0	0	0	0	1778	0	25	160189	100	160023	100	160020	500	5482616	1	40076	0	40038	40038	20007	0	6	20052	160120	200	160032	200	320064	40099	40038	1	1	160201	100	99	100	100	160000	100	4	2	0	0	0	0	0	1	1	1	10118	1	16	0	0	40462	0	160000	100	40096	40096	40039	40039	40096
160204	40038	311	0	0	0	0	0	0	58	0	1855	111	25	160108	100	160078	100	160023	500	1511724	1	40066	0	40074	40038	19977	0	6	19989	160123	200	160032	200	320064	40057	40063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40092	0	160000	100	40058	40039	40096	40039	40086
160204	40038	311	0	1	0	0	0	0	144	0	1936	3	25	160109	100	160009	100	160020	500	1280132	1	40070	0	40038	40141	19977	0	6	20025	160120	200	160032	200	320064	40085	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	3	0	1	1	1	10118	0	16	1	0	40082	0	160000	100	40039	40039	40086	40039	40039
160204	40038	311	0	0	0	0	0	0	128	0	1370	0	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40039	40057	19977	0	6	19989	160120	200	160032	200	320064	40099	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	1	16	1	1	40035	0	160000	100	40039	40100	40039	40096	40096
160204	40182	310	0	0	0	0	0	0	0	0	1770	0	25	160108	100	160078	100	160020	500	1280132	1	40076	0	40038	40057	19977	0	6	19990	160120	200	160032	200	320064	40039	40073	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	0	16	0	1	40035	0	160000	100	40040	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40074	322	0	0	0	0	0	0	67	0	25	160062	10	160000	10	160000	50	1280000	1	1	40019	40095	40095	19996	0	3	20018	160010	20	160000	20	320000	40038	40095	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	16	16	2	1	1	19	16	40035	15	5	0	160000	10	40039	40039	40039	40039	40039
160024	40038	322	0	0	0	0	0	0	73	111	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40095	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	17	16	2	1	1	19	21	40054	15	7	0	160000	10	40138	40039	40039	40039	40039
160024	40039	310	0	0	0	0	0	0	45	0	25	160010	10	160000	10	160000	50	1280000	1	1	40076	40095	40039	19996	0	3	20075	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	17	16	4	2	2	16	21	40035	30	10	0	160000	10	40039	40154	40096	40039	40039
160024	40038	323	0	0	0	0	0	0	63	0	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40065	40077	19996	1	3	20018	160010	20	160000	20	320000	40038	40057	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	1	1	14	16	1	1	1	15	19	40035	15	6	0	160000	10	40058	40039	40040	40039	40039
160024	40038	310	0	0	0	0	0	0	51	0	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40039	40065	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	3	1	20	16	2	1	1	19	19	40035	15	5	0	160000	10	40039	40040	40208	40039	40058
160024	40038	310	0	0	0	0	0	0	45	111	25	160011	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40057	40057	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	3	3	1	20	16	2	1	1	19	23	40035	15	5	0	160000	10	40039	40039	40039	40039	40039
160024	40038	310	0	0	3	0	0	0	46	0	25	160010	10	160000	10	160000	50	1319997	1	1	40019	40038	40038	19996	0	3	20095	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	6	2	2	20	16	4	2	2	19	15	40150	31	12	0	160000	10	40039	40058	40039	40039	40058
160024	40039	310	0	0	0	0	0	0	51	0	25	160010	10	160000	10	160000	50	1280000	0	1	40019	40038	40057	19997	0	3	20037	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	6	2	2	22	16	4	2	2	19	21	40035	30	10	0	160000	10	40039	40058	40039	40058	40039
160024	40057	310	0	0	0	0	0	0	45	0	25	160010	10	160000	10	160000	50	1280000	0	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40095	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	6	2	2	18	16	3	2	2	19	20	40035	30	10	42	160000	10	40039	40058	40039	40058	40039
160024	40057	311	0	1	12	0	78	0	52	0	104	160158	10	160000	10	160000	50	5519418	1	1	40179	40095	40100	19996	0	3	20018	160010	20	160000	20	320000	40039	40207	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	3	2	2	18	16	3	1	2	19	20	40054	31	140	0	160000	10	40039	40058	40040	40058	40101

XTN2 (2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations