Firestorm: XTN2 (4S) measurements

Code:

  xtn2 v0.8h, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	15	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	0	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	0	1000	2038	2038	2038	2038	2038
1004	2037	16	0	103	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	0	1000	2038	2038	2038	2038	2038
1004	2037	16	3	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	0	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	38	1	1	1787	0	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	0	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	0	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	0	1000	2038	2038	2038	2038	2038
1004	2037	15	12	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	0	1000	2038	2038	2038	2038	2038
1004	2037	16	0	104	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	0	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  xtn2 v0.8h, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	155	0	0	24	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	1	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10270	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20086	20038	20038
10204	20037	155	0	0	0	96	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	6	734	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	15	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20071	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	15	10	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  xtn2 v0.8h, v0.4s

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	155	12	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18731	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	29	6	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	7	6	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	8	6	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	61	19666	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	7	0	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	1	0	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	726	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	40	3	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	155	30	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	2	0	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	3	1	1	1	717	0	16	0	0	19801	10000	100	20038	20087	20038	20038	20038
10204	20037	156	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ab	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	156	0	0	0	726	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	49	0	75	2	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20085	156	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	12	103	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20225	155	0	0	0	128	19686	25	10010	10	10000	10	10000	50	2848785	0	20018	20037	20037	18443	3	18785	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	160	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	12	89	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	63	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	6	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	12	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	162	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  xtn2 v0.8h, v8.4s
  movi v1.16b, 0
  xtn2 v1.8h, v8.4s
  movi v2.16b, 0
  xtn2 v2.8h, v8.4s
  movi v3.16b, 0
  xtn2 v3.8h, v8.4s
  movi v4.16b, 0
  xtn2 v4.8h, v8.4s
  movi v5.16b, 0
  xtn2 v5.8h, v8.4s
  movi v6.16b, 0
  xtn2 v6.8h, v8.4s
  movi v7.16b, 0
  xtn2 v7.8h, v8.4s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	156	0	0	9	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	117	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	71	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	9	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	12	1	1	1	10119	16	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20072	155	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	0	20026	0	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10033	3	1	1	13	326	2	1	1	11	11	20042	15	0	160000	10	20046	20047	20280	20051	20046
160024	20045	155	0	60	86	25	80010	10	80000	10	80000	50	640000	1	0	0	20026	0	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10035	8	1	1	9	20	2	1	1	9	7	20042	15	0	160000	10	20046	20046	20217	20046	20046
160024	20045	155	0	0	44	25	80010	10	80000	10	80000	50	640000	1	0	0	20026	0	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10032	8	1	1	9	20	2	1	1	9	8	20043	15	0	160000	10	20046	20046	20248	20046	20046
160024	20045	155	0	0	86	25	80010	10	80000	10	80000	50	640000	1	0	0	20026	0	20045	20046	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	3	0	10032	8	6	1	10	20	2	1	1	11	11	20042	15	0	160000	10	20046	20046	20215	20046	20046
160024	20045	155	0	0	44	25	80010	10	80000	10	80000	50	640000	1	0	0	20026	0	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	3	10033	3	6	1	10	20	2	1	1	11	10	20042	15	0	160000	10	20046	20046	20379	20284	20046
160024	20045	155	0	0	44	25	80010	10	80000	10	80000	50	640000	0	1	0	20030	0	20049	20049	3	21	80010	20	80000	20	160000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	1	3	10035	11	2	2	11	24	4	2	2	9	8	20046	30	0	160000	10	20050	20050	20247	20046	20046
160024	20049	155	0	0	44	25	80010	10	80000	10	80000	50	640000	1	0	5	20026	0	20045	20045	3	21	80010	20	80000	20	160000	20045	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	12	10034	3	1	2	11	22	4	1	1	10	10	20046	15	0	160000	10	20046	20046	20233	20050	24956
160024	20045	163	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	0	20026	0	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10033	8	6	1	9	24	4	1	1	10	9	20042	15	0	160000	10	20046	20046	20504	20050	20050
160024	20049	156	0	0	44	25	80010	10	80000	10	80000	50	640000	1	0	5	20030	0	20049	20049	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	1	0	10035	8	6	2	11	20	2	1	2	10	8	20042	15	0	160000	10	20046	20046	20231	20050	20046
160024	20045	155	0	0	86	25	80010	10	80000	10	80000	50	640000	1	1	5	20026	0	20045	20045	3	21	80010	20	80000	20	160000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	2	0	1	3	10032	3	1	1	12	20	2	1	1	12	12	20042	15	0	160000	10	20046	20046	20741	20046	20046

Test 5: throughput

Count: 16

Code:

  xtn2 v0.8h, v16.4s
  xtn2 v1.8h, v16.4s
  xtn2 v2.8h, v16.4s
  xtn2 v3.8h, v16.4s
  xtn2 v4.8h, v16.4s
  xtn2 v5.8h, v16.4s
  xtn2 v6.8h, v16.4s
  xtn2 v7.8h, v16.4s
  xtn2 v8.8h, v16.4s
  xtn2 v9.8h, v16.4s
  xtn2 v10.8h, v16.4s
  xtn2 v11.8h, v16.4s
  xtn2 v12.8h, v16.4s
  xtn2 v13.8h, v16.4s
  xtn2 v14.8h, v16.4s
  xtn2 v15.8h, v16.4s

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	19	1e	37	3f	4e	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40136	311	1	0	1	0	0	0	55	71	0	25	160108	100	160058	100	160020	500	5519550	1	5	40019	40089	40060	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	5	1	0	1	16	1	1	40092	160000	100	40039	40086	40075	40039	40039
160204	40038	311	1	0	1	0	0	78	56	0	2	25	160158	100	160008	100	160020	500	5440188	1	5	40019	40038	40085	19998	0	6	19989	160120	200	160032	200	320064	40095	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	3	1	1	1	10118	5	0	0	1	16	1	1	40035	160000	100	40058	40039	40096	40096	40039
160204	40095	311	1	0	1	0	9	78	50	0	0	25	160178	100	160008	100	160020	500	5519550	1	0	40163	40038	40038	19977	0	6	20046	160120	200	160032	200	321262	40095	40039	1	1	160201	100	99	100	100	160000	100	0	14	0	0	1	1	1	10118	0	0	0	1	16	1	1	40054	160000	100	40064	40039	40096	40096	40039
160204	40095	310	1	0	1	0	0	0	56	71	0	25	160108	100	160008	100	160023	500	5440188	1	0	40066	40038	40085	19998	0	6	20036	160123	200	160032	200	320064	40038	40057	1	1	160201	100	99	100	100	160000	100	0	1	0	0	1	1	1	10118	0	0	0	1	16	1	1	40035	160000	100	40086	40039	40040	40058	40096
160204	40095	310	1	0	1	0	0	1	56	111	0	25	160108	100	160008	100	160020	500	1280132	1	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40095	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	0	0	1	16	1	1	40138	160000	100	40183	40040	40039	40039	40039
160204	40038	311	1	0	1	0	0	23	55	0	0	25	160108	100	160040	100	160020	500	1320129	1	0	40019	40038	40106	19977	0	6	19989	160120	200	160032	200	320064	40038	40057	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	0	0	1	16	1	1	40070	160000	100	40039	40096	40096	40039	40040
160204	40038	310	1	0	1	0	0	0	56	111	0	25	160108	100	160078	100	160020	500	5519550	1	0	40019	40095	40038	20007	0	6	19989	160120	200	160032	200	320064	40039	40057	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	0	0	1	16	1	1	40035	160000	100	40086	40039	40086	40075	40039
160204	40085	311	1	0	1	0	0	78	29	0	0	25	160108	100	160058	100	160023	500	1280132	0	0	40020	40095	40095	19977	0	6	19989	160121	200	160032	200	321762	40038	40057	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	0	0	1	16	1	1	40092	160000	100	40090	40064	40039	40096	40039
160204	40038	310	1	0	1	0	0	58	55	0	0	25	160140	100	160040	100	160021	500	1280132	1	0	40122	40038	40085	19998	0	6	19989	160120	200	160032	200	320064	40063	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	0	0	1	16	1	1	40138	160000	100	40039	40100	40039	40039	40040
160204	40038	311	1	0	1	0	0	0	29	0	0	25	160109	100	160008	100	160020	500	5519550	0	0	40076	40100	40038	20007	0	6	20046	160120	200	160032	200	320064	40038	40095	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	0	0	1	16	1	1	40092	160000	100	40096	40039	40096	40096	40096

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	311	0	0	0	0	0	0	0	0	74	45	25	160010	10	160000	10	160000	50	1280000	1	1	40134	40039	40077	19996	0	3	20073	160010	20	160000	20	320000	40095	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	11174	21	1	1	0	7	16	4	52	3	4	5	40035	20	8	160000	10	40039	40039	40058	40138	40039
160024	40063	310	0	0	0	0	0	0	0	78	73	0	25	160010	10	160078	10	160000	50	1280000	0	1	40019	40038	40038	20000	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	3	1	2	0	3	16	4	41	3	3	6	40036	20	8	160000	10	40096	40096	40039	40039	40039
160024	40038	311	0	0	0	0	0	12	0	23	45	0	25	160010	10	160144	10	160000	50	5480377	1	1	40019	40095	40038	19996	0	3	20018	160010	20	160000	20	320000	40039	40207	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	0	4	16	2	32	2	4	4	40035	20	8	160000	10	40039	40039	40096	40039	40096
160024	40038	310	0	0	0	0	0	0	0	27	45	111	25	160091	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	0	4	16	2	33	3	4	4	40035	20	8	160000	10	40039	40039	40039	40039	40096
160024	40077	311	0	0	0	0	0	0	0	78	70	0	25	160010	10	160000	10	160000	50	5519418	1	1	40134	40077	40038	19996	0	3	20075	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	6	2	1	0	6	16	2	35	2	9	7	40150	20	8	160000	10	40039	40039	40039	40039	40039
160024	40095	310	0	0	0	1	1	135	0	0	45	111	25	160010	10	160149	10	160000	50	5519418	1	1	40019	40077	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	6	1	1	0	7	16	38	4	1	7	8	40092	20	8	160000	10	40039	40039	40154	40101	40039
160024	40038	311	0	0	0	0	0	0	0	1	45	0	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40057	40039	19996	0	3	20037	160010	20	160000	20	320000	40038	40057	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	0	4	16	32	3	2	7	4	40035	40	16	160000	10	40039	40096	40039	40039	40039
160024	40095	310	0	0	0	0	0	12	0	81	67	111	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40124	19996	0	3	20018	160010	20	160000	20	320000	40039	40057	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	6	1	1	0	6	16	38	3	1	4	5	40092	20	8	160000	10	40039	40040	40040	40039	40039
160024	40038	311	0	0	0	0	0	0	0	0	51	0	25	160033	10	160078	10	160000	50	1280000	0	1	40118	40057	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40143	1	1	160021	10	9	10	10	160000	10	0	0	0	0	4	3	0	0	10024	6	2	2	0	3	16	50	5	1	7	9	40035	40	8	160000	10	40078	40096	40039	40039	40039
160024	40095	311	0	0	0	0	0	0	0	78	90	270	25	160010	10	160000	10	160000	50	1280000	1	1	40076	40095	40038	20026	0	3	20018	160010	20	160000	20	320000	40153	40095	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	6	2	2	0	3	16	40	5	1	4	4	40092	20	8	160000	10	40039	40039	40039	40096	40096

XTN2 (4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations