Firestorm: XTN2 (8H) measurements

Code:

  xtn2 v0.16b, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	3	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	103	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	24	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	81	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	1	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	12	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	82	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	6	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  xtn2 v0.16b, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	155	0	0	0	0	0	0	0	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	1	1	19825	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	0	559	19687	0	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	3	0	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	7	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	2	2	2	0	0	11683	2	841	4	65	1	2	19972	27	10000	100	20277	20276	20313	20279	20314
10204	20275	157	0	0	0	5	5	666	440	0	3480	19632	0	121	10197	141	10060	134	10760	650	2854095	0	20162	20266	20314	18438	31	18840	10894	212	10836	202	21660	20228	20278	6	1	10201	100	99	100	100	10000	100	2	2	0	2	0	9968	0	710	1	16	1	1	19791	0	10000	100	20038	20086	20134	20038	20180
10204	20037	155	0	0	0	0	0	12	0	0	61	19687	0	25	10100	100	10000	132	10456	624	2850166	0	20018	20183	20276	18447	29	18819	10740	214	10834	216	21500	20132	20276	6	1	10201	100	99	100	100	10000	100	2	0	2	0	0	5896	2	800	2	57	2	2	19971	25	10000	100	20279	20276	20324	20276	20276

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	9	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	9	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19823	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	123	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	1	0	707	2	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18453	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  xtn2 v0.16b, v0.8h

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	155	0	1	270	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	19787	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	89	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	61	19686	25	10100	104	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18741	10100	200	10008	202	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	179	19686	25	10100	100	10000	104	10000	500	2847521	1	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	1	124	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	19800	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	156	0	0	0	0	66	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	3	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	417	0	360	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	5	12	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	191	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	0	0	168	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	189	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	12	0	170	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	149	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  xtn2 v0.16b, v8.8h
  movi v1.16b, 0
  xtn2 v1.16b, v8.8h
  movi v2.16b, 0
  xtn2 v2.16b, v8.8h
  movi v3.16b, 0
  xtn2 v3.16b, v8.8h
  movi v4.16b, 0
  xtn2 v4.16b, v8.8h
  movi v5.16b, 0
  xtn2 v5.16b, v8.8h
  movi v6.16b, 0
  xtn2 v6.16b, v8.8h
  movi v7.16b, 0
  xtn2 v7.16b, v8.8h

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	156	0	0	0	0	0	0	0	0	0	0	176	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	1	16	0	0	20101	0	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	0	0	0	0	0	50	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	0	0	6	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	161	0	0	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20101	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	0	0	0	0	0	568	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	0	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	1	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20077	155	0	0	0	0	274	29	80010	10	80000	10	80000	50	640000	0	1	5	20040	0	20050	20059	3	21	80010	20	80201	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	10030	11	2	2	5	34	2	2	2	8	4	20056	40	2	160000	10	20060	20060	20051	20060	20060
160024	20050	156	0	0	0	0	120	29	80010	10	80000	10	80000	50	640000	0	1	5	20040	0	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	11	3	2	4	25	4	2	1	7	4	20056	41	1	160000	10	20060	20060	20060	20051	20052
160024	20059	155	0	0	0	0	50	29	80010	10	80000	10	80000	50	640000	0	1	5	20040	0	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	11	3	2	5	25	4	2	2	10	5	20047	21	1	160000	10	20051	20051	20051	20060	20051
160024	20050	156	0	0	0	0	44	29	80010	10	80000	10	80000	50	640000	1	1	5	20040	0	20050	20051	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10027	8	3	2	4	26	2	1	2	6	3	20047	40	2	160000	10	20051	20060	20051	20051	20052
160024	20050	156	0	0	0	0	44	28	80010	10	80000	10	80000	50	640000	1	1	5	20031	0	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10027	8	3	2	4	25	2	1	1	6	7	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20059	155	0	0	0	0	65	27	80010	10	80000	10	80000	50	640000	0	1	5	20040	0	20059	20050	3	21	80010	20	80000	20	160000	20059	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10027	8	3	1	4	25	2	1	1	8	5	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	156	0	0	0	0	44	27	80010	10	80000	10	80000	50	640000	0	1	0	20040	0	20050	20050	3	21	80010	20	80000	20	160000	20059	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10030	8	4	1	4	25	2	1	1	10	3	20047	20	2	160000	10	20060	20060	20060	20060	20061
160024	20050	155	0	0	0	0	159	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	0	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	8	5	1	4	34	2	1	1	7	5	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	155	0	0	0	9	50	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	0	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	8	5	1	6	34	2	1	1	9	6	20047	40	2	160000	10	20051	20051	20051	20051	20051
160024	20050	156	0	0	0	0	377	27	80010	10	80000	10	80000	50	640000	1	1	5	20040	0	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	8	5	1	3	25	2	1	1	9	5	20047	20	1	160000	10	20051	20051	20051	20051	20051

Test 5: throughput

Count: 16

Code:

  xtn2 v0.16b, v16.8h
  xtn2 v1.16b, v16.8h
  xtn2 v2.16b, v16.8h
  xtn2 v3.16b, v16.8h
  xtn2 v4.16b, v16.8h
  xtn2 v5.16b, v16.8h
  xtn2 v6.16b, v16.8h
  xtn2 v7.16b, v16.8h
  xtn2 v8.16b, v16.8h
  xtn2 v9.16b, v16.8h
  xtn2 v10.16b, v16.8h
  xtn2 v11.16b, v16.8h
  xtn2 v12.16b, v16.8h
  xtn2 v13.16b, v16.8h
  xtn2 v14.16b, v16.8h
  xtn2 v15.16b, v16.8h

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40126	311	0	0	0	0	0	0	93	0	0	0	139	0	25	160158	100	160008	100	160020	500	5598302	0	0	40019	40038	40141	19977	0	6	19989	160120	200	160032	200	320064	40038	40095	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40082	0	160000	100	40040	40039	40039	40142	40090
160204	40099	310	0	0	0	0	0	0	0	0	0	0	720	0	25	160108	100	160008	100	160020	500	1280132	0	1	40019	40095	40095	19998	0	6	19990	160120	200	160032	200	320064	40038	40095	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40092	0	160000	100	40058	40039	40064	40039	40096
160204	40038	311	0	0	0	0	0	0	33	0	147	0	56	111	25	160108	100	160078	100	160020	500	5565688	0	0	40122	40039	40039	19977	0	6	20092	160122	200	160032	200	320064	40038	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40138	0	160000	100	40096	40039	40096	40040	40039
160204	40095	310	0	0	0	0	0	0	0	0	78	0	47	111	25	160178	100	160078	100	160020	500	5519550	0	0	40044	40038	40073	19978	0	6	20050	160120	200	160032	200	320064	40038	40057	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40040	40040	40120
160204	40038	311	0	0	0	0	0	0	0	0	0	0	56	0	25	160108	100	160058	100	160020	500	1280132	0	0	40020	40038	40057	20068	0	6	19990	160122	200	160032	200	320064	40038	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40071	0	160000	100	40096	40096	40039	40096	40039
160204	40095	310	0	0	0	0	0	0	0	0	0	0	30	0	25	160178	100	160008	100	160020	500	3997565	0	0	40019	40038	40038	19977	0	6	20046	160121	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40138	0	160000	100	40223	40390	40316	40200	40241
160204	40299	312	1	1	1	0	0	0	0	730	35	1	1619	241	89	160326	100	160428	100	160358	500	1280132	0	0	40407	40345	40411	20164	22	19	20128	160524	200	160565	200	320456	40259	40370	4	1	160201	100	99	100	100	160000	100	0	0	3	0	0	3990	2	1	1	1	10439	0	204	0	0	41266	1	160000	100	41022	41397	41172	41854	41515
160204	41135	325	0	0	1	0	16	16	1989	1496	408	0	4812	1504	239	162287	100	161235	100	161759	544	2469485	0	0	40555	40796	40846	20492	0	68	20546	161764	200	161339	200	322742	40957	40690	11	1	160201	100	99	100	100	160000	100	0	2	0	2	2	6293	0	1	1	1	10371	0	139	0	0	40525	1	160000	100	40709	41057	41008	41054	40788
160204	40187	319	0	1	1	0	11	11	1452	968	180	0	3857	716	280	162234	102	161951	102	161965	511	2714606	0	0	40392	41076	40960	20291	33	80	20407	162173	206	161815	204	323848	40966	40419	15	1	160201	100	99	100	100	160000	100	0	0	0	0	2	2253	2	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40183	40039	40102
160204	40141	310	0	0	0	0	0	0	0	0	58	0	55	0	25	160158	100	160058	100	160020	500	5438423	0	0	40082	40095	40095	19977	0	6	20046	160120	200	160032	200	320064	40085	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40086	40039	40086	40039	40086

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40065	301	0	0	0	0	90	0	0	134	0	25	160010	10	160000	10	160000	50	1280000	2	1	0	40071	40039	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	11	5	2	8	16	4	2	2	6	8	40035	30	5	160000	10	40039	40085	40088	40067	40113
160024	40112	300	0	0	0	0	0	0	0	45	10	25	160010	10	160000	10	160000	50	1319998	0	1	0	40019	40078	40084	20015	0	3	20019	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	11	2	2	6	16	4	2	2	6	6	40098	30	10	160000	10	40039	40039	40039	40113	40074
160024	40039	300	0	0	0	0	0	0	0	66	0	25	160070	10	160060	10	160000	50	1280000	1	0	5	40019	40112	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40084	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	3	1	1	9	16	4	1	1	6	9	40084	15	6	160000	10	40144	40040	40039	40040	40039
160024	40038	300	1	0	0	0	36	0	0	257	149	25	160011	10	160028	10	160000	50	1319999	1	1	0	40019	40112	40039	19996	0	3	20019	160010	20	160000	20	320000	40038	40112	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	2	8	16	2	1	1	6	4	40035	15	5	160000	10	40059	40040	40039	40039	40039
160024	40039	299	0	0	0	0	0	0	28	67	10	25	160010	10	160000	10	160000	50	5516100	1	0	5	40019	40038	40057	20006	0	3	20018	160010	20	160000	20	320000	40038	40087	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	8	4	1	8	16	4	1	1	8	9	40109	15	12	160000	10	40039	40113	40039	40039	40065
160024	40038	300	0	0	0	0	0	0	60	73	70	25	160070	10	160060	10	160000	50	1280000	1	0	0	40019	40038	40039	20010	0	3	20079	160010	20	160000	20	320000	40057	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	2	5	16	2	1	1	8	8	40036	15	5	160000	10	40039	40085	40039	40085	40039
160024	40038	299	0	0	0	0	0	0	60	67	0	25	160010	10	160000	10	160000	50	5516100	0	1	0	40065	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40084	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	4	1	10	16	2	1	1	9	6	40035	15	5	160000	10	40040	40039	40085	40039	40085
160024	40038	300	0	0	0	0	57	0	106	67	70	25	160011	10	160045	10	160000	50	4728951	1	1	0	40065	40038	40038	20006	13	3	20092	160010	20	160000	20	320000	40038	40084	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	6	16	2	1	1	5	6	40035	15	5	160000	10	40040	40088	40065	40040	40040
160024	40112	300	0	0	0	0	0	0	1	46	0	25	160116	10	160000	10	160000	50	5519778	1	0	0	40020	40039	40038	19996	0	3	20018	160010	20	160000	20	320000	40064	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	8	4	1	8	16	2	1	1	5	6	40035	45	5	160000	10	40039	40040	40088	40040	40039
160024	40038	300	0	0	0	0	0	0	106	67	3	25	160055	10	160000	10	160112	50	1280000	1	0	5	40093	40038	40038	19996	0	3	20070	160010	20	160000	20	320000	40038	40087	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	4	1	5	16	2	1	1	6	6	40035	15	5	160000	10	40039	40076	40039	40040	40039

XTN2 (8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations