Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ZIP1 (vector, 16B)

Test 1: uops

Code:

  zip1 v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371600006116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371500008216872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203716000012416872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371600006116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371600006116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715000015616872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371600006116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371600006116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371700006116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371600016116872510001000100026468002018203720841572318951000100020002037203721100110000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  zip1 v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371550696119687251010010010000100100005002847680102001820037200371842231874510100200100002002000020037200371110201100991001001000010003071001161119791100001002003820038200382003820038
1020420037155006119687251010010010000100100005002847680102001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
1020420037155006119687251010010010000100100005002847680102001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
1020420037155006119687251010010010000100100005002847680102001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
1020420037155006119687251010010010000100100005002847680102001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
1020420037155006119687251010010010000100100005002847680102001820037200371842231874510100200100002002000020037200371110201100991001001000010010071001161119791100001002003820038200382003820038
1020420037155006119687251010010010000100100005002847680102001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002008620038200382003820038
1020420037155006119687251010010010000100100005002847680102001820037200371842231876310100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
10204200371550126119687251010010010000100100005002847680102001820037200371842231874510100200100002002000020037200371110201100991001001000010010071001161119791100001002003820038200382003820038
10204200371550015619687251010010010000100100005002847680102001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371557861196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037155661196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037155061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037155361196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037155961196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037155061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037155061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037155061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
10024200371550536196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
1002420037156061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  zip1 v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715500061196872510100100100001001000050028476801020018200372003718422318745101002001000020020000200372003711102011009910010010000100002930710011611197910100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680002001820037200371842231874510100200100002002000020037200371110201100991001001000010000100710011611197910100001002003820038200382003820038
1020420037155000726196872510100100100001001000050028476801020018200372003718422318745101002001000020020000200372003711102011009910010010000100004400710011611197910100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680042001820037200371842231874510100200100002002000020037200371110201100991001001000010000200710011611197910100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000710011611197910100001002003820038200382003820038
10204200371550008919687251010010010000100100005002847680002001820037200371842231874510100200100002002000020037200371110201100991001001000010000100710011611197910100001002003820038200382003820038
102042003715500010319687251010010010000100100005002847680002001820037200371842231874510100200100002002000020037200371110201100991001001000010000200710011611197910100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680002001820037200371842231874510100200100002002000020037200371110201100991001001000010000100710011611197911100001002003820038200382003820038
102042003715500013119687251010010010000100100005002847680042001820037200371842231874510100200100002002000020037200371110201100991001001000010000100710011611197910100001002003820038200382003820038
10204200371550006119687251010010010000100100005002847680002001820037200371842231874510100200100002002000020037200371110201100991001001000010000130710011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)abacc2cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715500107196872510023101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000064003163319785010000102003820038200382003820038
10024200371550061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000064003163319785010000102003820038200382003820038
100242003715500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010010093064003163319785010000102003820038200382003820038
10024200371560061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000200064003163319785010000102003820038200382003820038
100242003715500103196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000064003163319785010000102003820038200382003820038
10024200371550061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000009064003163319785010000102003820038200382003820038
10024200371560061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000109064003163319785010000102003820038200382003820038
1002420037161206119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000150064003163319785010000102003820038200382003820038
10024200371552061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000064003163319785010000102003820038200382003820038
10024200371552061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000064003163319785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  zip1 v0.16b, v8.16b, v9.16b
  zip1 v1.16b, v8.16b, v9.16b
  zip1 v2.16b, v8.16b, v9.16b
  zip1 v3.16b, v8.16b, v9.16b
  zip1 v4.16b, v8.16b, v9.16b
  zip1 v5.16b, v8.16b, v9.16b
  zip1 v6.16b, v8.16b, v9.16b
  zip1 v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420038155000006325801001008000010080000500640766120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511002161120035800001002003920092200392003920039
8020420038155000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511001161120035800001002003920039200392003920039
8020420038155000004025801001008009210080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511001161120035800001002003920039200392003920039
802042003815500100283425801001208000010080000500640000120019200382003899733999680100200800002001600002003820038218020110099100100800001000000000511001161120035800001002003920039200392003920039
8020420038156000006325801001008000010080000500640000020059200382003899733999680100200800002001600002003820038118020110099100100800001002200000511001161120035800001002003920039200392003920039
8020420038156100004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000030511001161120035800001002009220039200392003920039
8020420038155000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000020000511001161120076800001002003920039200392003920039
8020420038156000004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000000511001161120035800001002003920039200392003920039
80204200381550006040258010010080000100800005006400000200192003820038997331002380100200800002001600002003820038118020110099100100800001000000000511001161120035800001002003920039200392003920039
802042003815500090402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000004680511001161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471560003925800121280000108000060640000120019200382003899963100188001020800002016000020038200381180021109101080000100000005020316111200350080000102201520041200392003920039
80024200381550003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000005020216023200352080000102003920039200392003920039
80024200381550003925800101080000128000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000005020116011200350080000102003920039200392003920039
800242003815500041925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000005020116011200970080000102003920039200392003920039
80024200381550003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000005020116021200350080000102003920039200392003920039
80024200381550003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000005020116011200350080000102003920039200392003920039
800242003815600039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000050201160112003501780000102003920039200392003920039
80024200381550003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000005020116011200350080000102003920039200392003920039
800242003815500123925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100000005020116011200350080000102003920039200392003920039
800242003815600060925800121080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100001005020116011200350080000102003920039200392003920039