Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
zip1 v0.2d, v0.2d, v1.2d
movi v0.16b, 1 movi v1.16b, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 1.000
| retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 18 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule simd uop (54) | dispatch simd uop (57) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map simd uop (7e) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd alu (9a) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
| 1004 | 2037 | 16 | 0 | 0 | 0 | 61 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 0 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 2 | 16 | 1 | 1 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
| 1004 | 2037 | 15 | 0 | 0 | 0 | 61 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 0 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
| 1004 | 2037 | 15 | 0 | 0 | 0 | 61 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 1 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
| 1004 | 2037 | 16 | 0 | 0 | 0 | 61 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 0 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
| 1004 | 2037 | 16 | 0 | 0 | 0 | 61 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 1 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
| 1004 | 2037 | 17 | 0 | 0 | 0 | 61 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 0 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
| 1004 | 2037 | 15 | 0 | 0 | 0 | 61 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 0 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
| 1004 | 2037 | 16 | 0 | 0 | 12 | 61 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 0 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
| 1004 | 2037 | 16 | 0 | 0 | 0 | 61 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 1 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
| 1004 | 2037 | 15 | 0 | 0 | 0 | 251 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 0 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 73 | 1 | 16 | 1 | 1 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
Code:
zip1 v0.2d, v0.2d, v1.2d
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.0037
| retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | 1e | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10204 | 20037 | 155 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 1 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 155 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 1 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 155 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 1 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 3 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 156 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 1 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 0 | 10000 | 100 | 20038 | 20038 | 20231 | 20038 | 20038 |
| 10204 | 20037 | 155 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 1 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 156 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 1 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10125 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 155 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 1 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 155 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 1 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 155 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 1 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20085 | 20038 |
| 10204 | 20037 | 155 | 1 | 0 | 103 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 1 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10125 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 0 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
Result (median cycles for code): 2.0037
| retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | 19 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb miss (a1) | ld unit uop (a6) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10024 | 20037 | 150 | 0 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 150 | 0 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 150 | 0 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 102 | 640 | 3 | 16 | 3 | 3 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 151 | 0 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20084 | 18451 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 1 | 0 | 640 | 3 | 16 | 3 | 3 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 150 | 0 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 1 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 3 | 640 | 3 | 16 | 3 | 3 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 150 | 0 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 1 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 99 | 640 | 3 | 16 | 3 | 3 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 150 | 0 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 1 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 2 | 0 | 640 | 3 | 16 | 3 | 3 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10025 | 20037 | 150 | 0 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 1 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 117 | 640 | 3 | 16 | 3 | 3 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20122 |
| 10024 | 20037 | 150 | 0 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 1 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 150 | 0 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 1 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 31 | 9 | 640 | 3 | 16 | 2 | 3 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
Code:
zip1 v0.2d, v1.2d, v0.2d
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.0037
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 19 | 1e | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | ld unit uop (a6) | l1d cache writeback (a8) | aa | ac | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10204 | 20037 | 156 | 0 | 0 | 0 | 0 | 0 | 3565 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 0 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 156 | 0 | 1 | 0 | 0 | 0 | 285 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 1 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 155 | 0 | 0 | 0 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 0 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 156 | 0 | 0 | 0 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 0 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 155 | 0 | 0 | 0 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 1 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 161 | 0 | 0 | 0 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 0 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 155 | 0 | 0 | 0 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 0 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 155 | 0 | 0 | 0 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 1 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 155 | 0 | 0 | 0 | 0 | 270 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 0 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10204 | 20037 | 155 | 0 | 0 | 0 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 0 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
Result (median cycles for code): 2.0037
| retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 1e | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10024 | 20037 | 155 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 1 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 1 | 3 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 156 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 155 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 156 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 1 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 2 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 156 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20085 | 20038 |
| 10024 | 20037 | 155 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10169 | 20 | 20000 | 20086 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 1 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 155 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 156 | 0 | 0 | 103 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 155 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 1 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
| 10024 | 20037 | 155 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 1 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20132 | 20038 |
Count: 8
Code:
zip1 v0.2d, v8.2d, v9.2d zip1 v1.2d, v8.2d, v9.2d zip1 v2.2d, v8.2d, v9.2d zip1 v3.2d, v8.2d, v9.2d zip1 v4.2d, v8.2d, v9.2d zip1 v5.2d, v8.2d, v9.2d zip1 v6.2d, v8.2d, v9.2d zip1 v7.2d, v8.2d, v9.2d
movi v8.16b, 9 movi v9.16b, 10
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.2505
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | simd prf full (72) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80204 | 20058 | 155 | 0 | 0 | 0 | 0 | 15 | 0 | 40 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20019 | 20038 | 20038 | 9973 | 0 | 3 | 9996 | 80100 | 200 | 80000 | 200 | 160000 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 2 | 16 | 1 | 1 | 20035 | 0 | 0 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80204 | 20038 | 155 | 0 | 0 | 0 | 0 | 0 | 0 | 40 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 1 | 20019 | 20038 | 20038 | 9973 | 0 | 3 | 9996 | 80100 | 200 | 80000 | 200 | 160000 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 20035 | 0 | 0 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80204 | 20038 | 156 | 0 | 0 | 0 | 0 | 0 | 0 | 283 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20019 | 20038 | 20038 | 9973 | 0 | 3 | 9996 | 80100 | 200 | 80000 | 200 | 160000 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0 | 5110 | 1 | 16 | 1 | 1 | 20035 | 0 | 0 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80204 | 20038 | 156 | 0 | 0 | 0 | 0 | 255 | 0 | 40 | 25 | 80100 | 100 | 80094 | 100 | 80000 | 500 | 640000 | 0 | 20019 | 20038 | 20038 | 9973 | 0 | 3 | 9996 | 80100 | 200 | 80000 | 200 | 160000 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 20035 | 0 | 0 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80204 | 20038 | 155 | 0 | 0 | 0 | 0 | 0 | 0 | 40 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20019 | 20038 | 20038 | 9973 | 0 | 3 | 9996 | 80100 | 200 | 80000 | 200 | 160000 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 20035 | 0 | 0 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80204 | 20038 | 156 | 0 | 0 | 0 | 0 | 0 | 0 | 40 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20019 | 20038 | 20038 | 9973 | 0 | 3 | 9996 | 80100 | 200 | 80000 | 200 | 160000 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 20035 | 0 | 0 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80204 | 20038 | 161 | 0 | 0 | 0 | 0 | 0 | 0 | 316 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 1 | 12831 | 20038 | 20038 | 9973 | 0 | 3 | 9996 | 80100 | 200 | 80000 | 200 | 160000 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 20035 | 0 | 0 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80204 | 20038 | 155 | 0 | 0 | 0 | 0 | 0 | 0 | 40 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 1 | 20019 | 20038 | 20038 | 9973 | 0 | 3 | 9996 | 80100 | 200 | 80000 | 200 | 160000 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 20035 | 0 | 0 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80204 | 20038 | 155 | 0 | 0 | 0 | 0 | 0 | 0 | 40 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 1 | 20019 | 20038 | 20038 | 9973 | 0 | 3 | 9996 | 80100 | 200 | 80000 | 200 | 160000 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 20035 | 0 | 0 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80204 | 20038 | 156 | 0 | 0 | 0 | 0 | 0 | 0 | 40 | 25 | 80100 | 100 | 80000 | 100 | 80000 | 500 | 640000 | 0 | 20019 | 20038 | 20038 | 9973 | 0 | 3 | 9996 | 80100 | 200 | 80000 | 200 | 160000 | 20038 | 20038 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 20035 | 0 | 0 | 80000 | 100 | 20039 | 20039 | 20039 | 20039 | 20039 |
Result (median cycles for code divided by count): 0.2505
| retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80024 | 20048 | 155 | 0 | 0 | 24 | 104 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20019 | 0 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 160000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 5020 | 7 | 16 | 6 | 7 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80024 | 20038 | 155 | 0 | 0 | 39 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20019 | 0 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 160000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 5020 | 8 | 16 | 6 | 5 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80024 | 20038 | 150 | 0 | 0 | 66 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20019 | 0 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 160000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 5020 | 5 | 16 | 5 | 6 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80024 | 20038 | 150 | 0 | 0 | 0 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20019 | 0 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 160000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 16 | 0 | 5020 | 5 | 16 | 4 | 6 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80024 | 20038 | 150 | 0 | 0 | 33 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20019 | 0 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 160000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 5020 | 6 | 16 | 8 | 8 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80024 | 20038 | 150 | 0 | 0 | 27 | 506 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20019 | 0 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 160000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 1 | 0 | 5056 | 6 | 16 | 6 | 8 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80024 | 20038 | 150 | 0 | 0 | 24 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20019 | 0 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 160000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 5020 | 6 | 16 | 6 | 5 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80024 | 20038 | 150 | 0 | 1 | 21 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20019 | 0 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 160000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 5020 | 6 | 16 | 6 | 5 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80024 | 20038 | 150 | 0 | 0 | 12 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 20019 | 0 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 160000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 5020 | 6 | 16 | 5 | 6 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |
| 80024 | 20038 | 150 | 0 | 0 | 342 | 39 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 20019 | 0 | 20038 | 20038 | 9996 | 3 | 10018 | 80010 | 20 | 80000 | 20 | 160000 | 20038 | 20038 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 10 | 0 | 0 | 5020 | 5 | 16 | 6 | 5 | 20035 | 80000 | 10 | 20039 | 20039 | 20039 | 20039 | 20039 |