Firestorm: ZIP2 (vector, 4S) measurements

Code:

  zip2 v0.4s, v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1089	2000	2037	2037	1	1	1001	1000	0	0	73	3	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	1	0	825	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	103	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	2	16	2	2	1787	1000	2074	2038	2038	2038	2038
1004	2037	16	0	0	145	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	3	24	2	2	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->2

Code:

  zip2 v0.4s, v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	155	0	30	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18429	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20085	20038	20038	20038	20038
10204	20037	155	0	504	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18429	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	375	346	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18429	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	536	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18429	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	6	0	1	1	1	717	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	345	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18796	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	213	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	324	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	18	962	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	72	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10585	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	155	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	3	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	0	0	0	0	0	0	536	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	3	0	0	640	5	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	0	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	0	0	0	114	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	2	16	2	2	19785	0	10000	10	20038	20071	20038	20038	20038
10024	20037	155	0	0	0	0	0	18	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20181	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	2144	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	5	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	5	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->3

Code:

  zip2 v0.4s, v1.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	185	0	0	103	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	81	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20085	20038	20038
10204	20037	185	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	75	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	185	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	185	9	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	84	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	173	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	57	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	174	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	84	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	173	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	63	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	173	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	3	3	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	161	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	161	12	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	1	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	155	0	0	0	0	0	108	0	61	19687	25	10010	10	10000	10	10000	71	2852812	0	20166	20273	20274	18465	26	18840	10619	26	10730	20	21662	20273	20273	6	1	10021	10	9	10	10	10000	10	2	0	2	1	4	11855	0	0	749	2	56	4	4	19971	4	10000	10	20276	20274	20228	20274	20229
10024	20274	157	0	1	1	5	5	672	528	3182	19632	118	10073	11	10060	13	10708	71	2854095	0	20198	20274	20226	18458	29	18879	10926	22	10990	22	22012	20319	20324	7	1	10021	10	9	10	10	10000	10	2	0	0	0	0	12765	4	0	789	2	81	4	3	20040	3	10000	10	20132	20275	20323	20323	20322
10024	20320	156	0	0	1	0	1	663	352	61	19687	44	10010	10	10000	10	10152	50	2847680	0	20018	20085	20037	18444	3	18767	10010	20	10168	20	20000	20085	20084	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	0	706	3	49	2	4	19929	4	10000	10	20321	20276	20085	20312	20134
10024	20323	157	1	0	0	0	0	426	0	217	19621	81	10049	15	10024	13	10000	67	2852812	0	20198	20037	20324	18444	25	18804	10620	20	11005	20	21624	20086	20275	7	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	0	640	3	16	3	5	20039	2	10000	10	20179	20180	20371	20085	20217
10024	20272	163	0	0	1	7	5	27	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	37	18860	11076	20	10499	24	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	0	0	0	0	654	2	96	3	2	19895	4	10000	10	20319	20134	20227	20274	20322
10024	20085	163	0	1	1	0	0	0	0	4561	19687	96	10060	13	10048	10	10000	72	2851529	1	20306	20324	20319	18462	25	18897	11060	20	10000	20	20356	20037	20085	2	1	10021	10	9	10	10	10000	10	9	2	3	0	0	8158	0	0	745	3	57	5	3	20094	4	10000	10	20038	20038	20038	20038	20038
10024	20037	161	0	0	0	0	2	399	176	145	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	12	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	0	0	0	0	0	738	19667	43	10025	10	10000	10	10000	50	2847680	1	20021	20037	20037	18450	3	18767	10010	20	10000	20	20338	20085	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19823	0	10000	10	20084	20038	20038	20038	20038
10024	20084	156	0	0	0	0	0	3	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  zip2 v0.4s, v8.4s, v9.4s
  zip2 v1.4s, v8.4s, v9.4s
  zip2 v2.4s, v8.4s, v9.4s
  zip2 v3.4s, v8.4s, v9.4s
  zip2 v4.4s, v8.4s, v9.4s
  zip2 v5.4s, v8.4s, v9.4s
  zip2 v6.4s, v8.4s, v9.4s
  zip2 v7.4s, v8.4s, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20059	155	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	3	0	0	0	5110	3	16	1	1	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	156	0	0	0	0	0	1022	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	9	0	40	25	80100	100	80000	100	80000	500	640000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	2	1	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	63	25	80100	100	80000	100	80000	500	640000	0	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	156	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	80000	100	20039	20039	20039	20039	20039
80204	20038	155	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	1	20019	20038	20038	9973	3	9996	80100	200	80000	200	160000	20038	20038	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	20035	80000	100	20039	20039	20039	20039	20039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20039	155	0	514	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	156	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	12	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	640000	20019	20089	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	3	39	25	80010	10	80000	10	80108	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20035	0	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	39	25	80010	10	80000	10	80000	50	640000	20019	20038	20038	9996	3	10018	80010	20	80000	20	160000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	5020	1	16	1	1	20035	0	80000	10	20039	20039	20039	20039	20039

ZIP2 (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations