Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ZIP2 (vector, 8B)

Test 1: uops

Code:

  zip2 v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037153103168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680120222037203715723189510001000200020372037111001100000073116111850100020382038203820382038
1004203716061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  zip2 v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155000000821968725101821001004810010000500284768015200182003720037184223187451010020010000200200002003720037111020110099100100100001000001601969710521161119791100001002003820038200382003820038
102042003715511000061196872510100100100001001000050028476801520018200372003718422318745101002001000020020000200372003711102011009910010010000100000000710521161119791100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801020018200372003718422318745101002001000020020000200372003711102011009910010010000100000200738521161119791100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801520018200372003718422318745101002001000020020000200372003711102011009910010010000100000000710521161119791100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801520018200372003718422318745101002001000020020000200372003711102011009910010010000100000000710521161119791100001002003820038200382003820038
102042003715600000061196872510100100100001001000050028476801520018200372003718422318745101002001000020020000200372003711102011009910010010000100000103710521161119791100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801520018200372003718422318745101002001000020020000200372003711102011009910010010000100000400710521161119791100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801520018200372003718422318745101002001000020020000200372003711102011009910010010000100000100710521161119791100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801520018200372003718422318745101002001000020020000200372003711102011009910010010000100000500710521161119791100001002003820038200382003820038
102042003715500000061196872510100100100001001000050028476801520018200372003718422318745101002001000020020000200372003711102011009910010010000100000200710521161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000106000640416431978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200183200372003718444318767100102010000202000020037200371110021109101010000100030640316341978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100030640416431978510000102003820038200382003820038
10024200371490061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000107000640316341978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100004640416341978510000102003820038200382003820038
10024200371910061196762510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000108000640416341978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100000640316341978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100000640416431978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000102000640416441978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000101400640416431978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  zip2 v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)030e1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715500168196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002008320038200382003820038
10204200371550061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371550061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715500103196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000071011611198470100001002003820038200382003820038
10204200371550061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001001071011611197910100001002003820038200382003820038
10204200371550061196872510100100100121001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371550061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371550061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371550061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197960100001002003820038200382003820038
102042003715600212196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371550008919687251001010100001010000502847680120018200372017818444318767100102010000202000020037200371110021109101010000100006640316331978510000102003820038200382003820038
100242003715600126119687251001010100001010000502847680020018200372003718444318767100102010167202033820085200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371561006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
100242022715500126119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
100242003715600126119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371550006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371560006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100100640316331978510000102003820038200382003820038
100242003715500027219687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371550006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371550006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038202262003820038

Test 4: throughput

Count: 8

Code:

  zip2 v0.8b, v8.8b, v9.8b
  zip2 v1.8b, v8.8b, v9.8b
  zip2 v2.8b, v8.8b, v9.8b
  zip2 v3.8b, v8.8b, v9.8b
  zip2 v4.8b, v8.8b, v9.8b
  zip2 v5.8b, v8.8b, v9.8b
  zip2 v6.8b, v8.8b, v9.8b
  zip2 v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)030918191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815600000712580108100800081008002050064013202001902003820038997769989801202008003220016006420038200381180201100991001008000010000111511801600200350800001002003920039200392003920039
802042003815500000292580108100800081008002050064013202001902003820038997769989801202008003220016006420038200381180201100991001008000010000111511801600200350800001002003920039200392003920039
802042003815500000292580108100800081008002050064013212001902003820038997769989801202008003220016006420038200381180201100991001008000010000111511801600200350800001002003920039200392003920039
802042003815500000292580108100800081008002050064013202001902003820038997769989801202008003220016006420038200381180201100991001008000010000111511801600200350800001002003920039200392003920039
8020420038155000120292580108100800081008002050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
8020420038155000007052580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
802042003815500000402580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
802042003815500000402580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
802042003815500000402580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
802042003815500000402580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048156039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001015020116112003580000102003920039200392003920039
8002420038155081258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
8002420038156039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
80024200381550704258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
8002420038155039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
80024200381561239258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
8002420038155039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
8002420038155039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039
80024200381550234258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001015020116112003580000102003920039200392003920039
80024200381550209258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001005020116112003580000102003920039200392003920039