Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
add d0, d0, d1
movi v0.16b, 1 movi v1.16b, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.001
Load/store unit issues: 0.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch simd uop (57) | ldst uops in schedulers (5b) | dispatch uop (78) | map simd uop (7e) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) |
1004 | 2033 | 1001 | 1 | 1000 | 1000 | 50248 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 2033 | 1001 | 1 | 1000 | 1000 | 50248 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 2033 | 1001 | 1 | 1000 | 1000 | 50248 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 2033 | 1001 | 1 | 1000 | 1000 | 50248 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 2033 | 1001 | 1 | 1000 | 1000 | 50248 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 2033 | 1001 | 1 | 1000 | 1000 | 50248 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 2033 | 1001 | 1 | 1000 | 1000 | 50248 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 2033 | 1001 | 1 | 1000 | 1000 | 50248 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 2033 | 1001 | 1 | 1000 | 1000 | 50248 | 1000 | 1000 | 2000 | 1 | 1000 |
1004 | 2033 | 1001 | 1 | 1000 | 1000 | 50248 | 1000 | 1000 | 2000 | 1 | 1000 |
Code:
add d0, d0, d1
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.0033
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10006 | 200 | 20012 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20096 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
Result (median cycles for code): 2.0033
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
Code:
add d0, d1, d0
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.0033
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10006 | 200 | 20012 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20012 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20096 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
10204 | 20033 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 509248 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
Result (median cycles for code): 2.0033
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509247 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
10024 | 20033 | 10021 | 21 | 10000 | 20 | 10000 | 70 | 509248 | 10020 | 20 | 10000 | 20 | 20000 | 11 | 10000 | 10 |
Count: 8
Code:
add d0, d8, d9 add d1, d8, d9 add d2, d8, d9 add d3, d8, d9 add d4, d8, d9 add d5, d8, d9 add d6, d8, d9 add d7, d8, d9
movi v8.16b, 9 movi v9.16b, 10
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5004
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
80204 | 40057 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320044 | 80110 | 200 | 80014 | 200 | 160026 | 1 | 80000 | 100 |
80204 | 40044 | 80107 | 101 | 80006 | 100 | 80010 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 160024 | 1 | 80000 | 100 |
80204 | 40034 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 160024 | 1 | 80000 | 100 |
80204 | 40034 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 160024 | 1 | 80000 | 100 |
80204 | 40034 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 160024 | 1 | 80000 | 100 |
80204 | 40034 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 160024 | 1 | 80000 | 100 |
80204 | 40034 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 160024 | 1 | 80000 | 100 |
80204 | 40034 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 160124 | 1 | 80000 | 100 |
80204 | 40034 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320044 | 80110 | 200 | 80013 | 200 | 160024 | 1 | 80000 | 100 |
80204 | 40034 | 80105 | 101 | 80004 | 100 | 80008 | 300 | 320036 | 80108 | 200 | 80012 | 200 | 160024 | 1 | 80000 | 100 |
Result (median cycles for code divided by count): 0.5004
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
80024 | 40258 | 80027 | 21 | 80006 | 20 | 80010 | 67 | 320052 | 80032 | 20 | 80018 | 20 | 160000 | 11 | 80000 | 10 |
80024 | 40034 | 80021 | 21 | 80000 | 20 | 80000 | 65 | 320000 | 80020 | 20 | 80000 | 20 | 160000 | 11 | 80000 | 10 |
80024 | 40034 | 80021 | 21 | 80000 | 20 | 80000 | 65 | 320000 | 80020 | 20 | 80000 | 20 | 160000 | 11 | 80000 | 10 |
80024 | 40034 | 80021 | 21 | 80000 | 20 | 80000 | 65 | 320000 | 80020 | 20 | 80000 | 20 | 160000 | 11 | 80000 | 10 |
80024 | 40034 | 80021 | 21 | 80000 | 20 | 80000 | 65 | 320000 | 80020 | 20 | 80000 | 20 | 160000 | 11 | 80000 | 10 |
80024 | 40036 | 80021 | 21 | 80000 | 20 | 80000 | 65 | 320000 | 80020 | 20 | 80000 | 20 | 160000 | 11 | 80000 | 10 |
80024 | 40034 | 80021 | 21 | 80000 | 20 | 80000 | 65 | 320000 | 80020 | 20 | 80000 | 20 | 160000 | 11 | 80000 | 10 |
80024 | 40034 | 80021 | 21 | 80000 | 20 | 80000 | 65 | 320000 | 80020 | 20 | 80000 | 20 | 160000 | 11 | 80000 | 10 |
80025 | 40069 | 80063 | 21 | 80042 | 20 | 80054 | 65 | 320000 | 80020 | 20 | 80000 | 20 | 160000 | 11 | 80000 | 10 |
80024 | 40034 | 80021 | 21 | 80000 | 20 | 80000 | 65 | 320000 | 80020 | 20 | 80000 | 20 | 160000 | 11 | 80000 | 10 |